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| DS26401 Octal T1/E1/J1 Framer www.maxim-ic.com GENERAL DESCRIPTION The DS26401 is an octal, software-selectable T1, E1 or J1 framer. It is composed of eight framer/formatters and a system (backplane) interface. Each framer has an HDLC controller that can be mapped to any DS0 or FDL (T1)/Sa (E1) bit. The DS26401 also includes a full-feature BERT device, which can be used with any of the eight T1/E1 ports, and an internal clock adapter useful for creating synchronous, high frequency backplane timing. The DS26401 is controlled through an 8-bit parallel port that can be configured for nonmultiplexed Intel or Motorola operation. FEATURES 8 Independent, Full-Featured T1/E1/J1 Framers/Formatters Independent Transmit and Receive Paths Flexible Signaling Extraction and Insertion Alarm Detection and Insertion Transmit Synchronizer AMI, B8ZS, HDB3, NRZ Line Coding Performance Monitor Counters BOC Message Controller (T1) Two-Frame Elastic Store Buffers for Each Transmitter and Receiver One HDLC Controller per Framer RAI-CI and AIS-CI Support Full-Feature BERT can be Mapped to Any Port Flexible TDM Backplane Supports Bus Rates from 1.544MHz to 16.384MHz Internal Clock Generator (CLAD) Supplies 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz JTAG Test Port Single 3.3V Supply with 5V Tolerant Inputs 17mm x 17mm, 256-Pin BGA (1.00mm Pitch) APPLICATIONS Line Cards Add-Drop Multiplexers DSLAMs Timing Systems PBXs Switches Central Office Equipment Go to www.maxim-ic.com/telecom for a complete list of Telecommunications data sheets, evaluation kits, application notes, and software downloads. Routers IMA ATM WAN Interface Customer-Premise Equipment ORDERING INFORMATION PART DS26401 DS26401N TEMP RANGE 0C to +70C -40C to +85C PIN-PACKAGE 256 BGA 256 BGA Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. 1 REV: 072403 DS26401 Octal T1/E1/J1 Framer TABLE OF CONTENTS 1. 2. 2.1 2.2 2.3 2.4 2.5 APPLICABLE STANDARDS ........................................................................................................7 FEATURES ..................................................................................................................................8 FRAMER/FORMATTER .....................................................................................................................................8 SYSTEM INTERFACE........................................................................................................................................8 HDLC CONTROLLERS ....................................................................................................................................9 TEST AND DIAGNOSTICS .................................................................................................................................9 CONTROL PORT..............................................................................................................................................9 3. 4. 5. 5.1 5.2 5.3 5.4 5.5 BLOCK DIAGRAMS...................................................................................................................10 SIGNAL LIST (SORTED BY SIGNAL NAME) ............................................................................13 SIGNAL DESCRIPTIONS...........................................................................................................17 RECEIVE FRAMER SIGNALS...........................................................................................................................17 TRANSMIT FRAMER SIGNALS.........................................................................................................................19 PARALLEL CONTROL PORT............................................................................................................................20 SYSTEM INTERFACE......................................................................................................................................21 TEST............................................................................................................................................................22 6. 7. 7.1 7.2 7.3 7.4 REGISTER MAP.........................................................................................................................23 GLOBAL FUNCTIONS ...............................................................................................................24 GLOBAL REGISTERS .....................................................................................................................................24 GLOBAL REGISTER DESCRIPTION AND OPERATION ........................................................................................25 IBO MULTIPLEXER........................................................................................................................................27 INTERRUPT TREE..........................................................................................................................................37 8. 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.16 8.17 8.18 8.19 8.20 8.21 8.22 T1 RECEIVER ............................................................................................................................38 T1 RECEIVER REGISTER MAP .......................................................................................................................38 T1 RECEIVE FRAMER DESCRIPTION AND OPERATION.....................................................................................43 RECEIVE MASTER-MODE REGISTER ..............................................................................................................44 INTERRUPT INFORMATION REGISTER .............................................................................................................44 T1 RECEIVE CONTROL REGISTERS ...............................................................................................................45 H.100 (CT BUS) COMPATIBILITY...................................................................................................................50 T1 RECEIVE STATUS AND INFORMATION ........................................................................................................52 T1 RECEIVE-SIDE DIGITAL MILLIWATT CODE GENERATION ............................................................................63 T1 ERROR COUNT REGISTERS......................................................................................................................64 DS0 MONITORING FUNCTION ....................................................................................................................69 T1 RECEIVE SIGNALING OPERATION..........................................................................................................70 T1 RECEIVE PER-CHANNEL IDLE CODE INSERTION ....................................................................................76 RECEIVE-CHANNEL BLOCKING OPERATION ................................................................................................77 RECEIVE ELASTIC STORES OPERATION .....................................................................................................78 FRACTIONAL T1 SUPPORT (GAPPED-CLOCK MODE)...................................................................................82 T1 BIT-ORIENTED CODE (BOC) CONTROLLER...........................................................................................83 RECEIVE SLC-96 OPERATION...................................................................................................................85 RECEIVE FDL ...........................................................................................................................................86 PROGRAMMABLE IN-BAND LOOP-CODE DETECTION ...................................................................................87 RECEIVE HDLC CONTROLLER...................................................................................................................92 INTERLEAVED PCM BUS OPERATION (IBO) .............................................................................................100 INTERFACING THE T1 RX FRAMER TO THE BERT .....................................................................................102 9. 9.1 2 T1 TRANSMIT ..........................................................................................................................104 T1 TRANSMIT REGISTER MAP .....................................................................................................................104 DS26401 Octal T1/E1/J1 Framer T1 TRANSMIT FORMATTER DESCRIPTION AND OPERATION...........................................................................108 9.2 9.3 TRANSMIT-MASTER MODE REGISTER ..........................................................................................................109 9.4 INTERRUPT INFORMATION REGISTERS .........................................................................................................109 9.5 T1 TRANSMIT CONTROL REGISTERS ...........................................................................................................110 9.6 T1 TRANSMIT STATUS AND INFORMATION ....................................................................................................115 9.7 T1 PER-CHANNEL LOOPBACK .....................................................................................................................118 9.8 T1 TRANSMIT DS0 MONITORING FUNCTION ................................................................................................119 9.9 T1 TRANSMIT SIGNALING OPERATION .........................................................................................................120 9.10 T1 TRANSMIT PER-CHANNEL IDLE CODE INSERTION ................................................................................123 9.11 T1 TRANSMIT CHANNEL BLOCKING REGISTERS........................................................................................124 9.12 T1 TRANSMIT ELASTIC STORES OPERATION ............................................................................................125 ELASTIC STORE DELAY AFTER INITIALIZATION ........................................................................................................126 9.13 FRACTIONAL T1 SUPPORT (GAPPED CLOCK MODE) .................................................................................129 9.14 T1 TRANSMIT BIT ORIENTED CODE (BOC) CONTROLLER .........................................................................130 9.15 T1 TRANSMIT FDL..................................................................................................................................131 9.16 TRANSMIT SLC-96 OPERATION ..............................................................................................................132 9.17 TRANSMIT HDLC CONTROLLER...............................................................................................................133 9.18 HDLC TRANSMIT EXAMPLE.....................................................................................................................141 9.19 PROGRAMMABLE IN-BAND LOOP-CODE GENERATOR................................................................................142 9.20 INTERLEAVED PCM BUS OPERATION (IBO) .............................................................................................144 9.21 INTERFACING THE T1 TX FORMATTER TO THE BERT................................................................................146 9.22 T1 TRANSMIT SYNCHRONIZER.................................................................................................................148 10. E1 RECEIVER ..........................................................................................................................150 10.1 E1 RECEIVER REGISTER MAP .................................................................................................................150 10.2 E1 RECEIVE FRAMER DESCRIPTION AND OPERATION ...............................................................................155 10.3 RECEIVE MASTER MODE REGISTER.........................................................................................................156 10.4 INTERRUPT INFORMATION REGISTERS......................................................................................................157 10.5 E1 RECEIVE CONTROL REGISTERS .........................................................................................................158 10.6 H.100 (CT BUS) COMPATIBILITY.............................................................................................................162 10.7 E1 RECEIVE STATUS AND INFORMATION ..................................................................................................164 10.8 E1 ERROR COUNT REGISTERS................................................................................................................175 10.9 DS0 MONITORING FUNCTION ..................................................................................................................181 10.10 E1 RECEIVE SIGNALING OPERATION........................................................................................................182 10.11 E1 RECEIVE PER-CHANNEL IDLE CODE INSERTION ..................................................................................187 10.12 RECEIVE CHANNEL BLOCKING OPERATION...............................................................................................188 10.13 RECEIVE ELASTIC STORES OPERATION ...................................................................................................189 ELASTIC STORE DELAY AFTER INITIALIZATION ........................................................................................................192 10.14 FRACTIONAL E1 SUPPORT (GAPPED CLOCK MODE) .................................................................................193 10.15 ADDITIONAL SA-BIT AND SI-BIT RECEIVE OPERATION (E1 MODE).............................................................194 10.16 RECEIVE HDLC CONTROLLER.................................................................................................................200 HDLC RECEIVE EXAMPLE .....................................................................................................................................207 10.17 INTERLEAVED PCM BUS OPERATION (IBO) .............................................................................................208 10.18 INTERFACING THE E1 RX FRAMER TO THE BERT .....................................................................................210 11. E1 TRANSMIT..........................................................................................................................212 E1 TRANSMIT REGISTER MAP .................................................................................................................212 E1 TRANSMIT FORMATTER DESCRIPTION AND OPERATION .......................................................................216 TRANSMIT MASTER MODE REGISTER.......................................................................................................217 INTERRUPT INFORMATION REGISTERS......................................................................................................218 E1 TRANSMIT CONTROL REGISTERS .......................................................................................................219 AUTOMATIC ALARM GENERATION ............................................................................................................221 G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY)......................................................................223 E1 TRANSMIT STATUS AND INFORMATION ................................................................................................225 PER-CHANNEL LOOPBACK.......................................................................................................................228 E1 TRANSMIT DS0 MONITORING FUNCTION.............................................................................................229 E1 TRANSMIT SIGNALING OPERATION......................................................................................................230 E1 TRANSMIT PER-CHANNEL IDLE CODE INSERTION ................................................................................233 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 11.11 11.12 3 DS26401 Octal T1/E1/J1 Framer E1 TRANSMIT CHANNEL BLOCKING REGISTERS .......................................................................................234 11.13 11.14 E1 TRANSMIT ELASTIC STORES OPERATION ............................................................................................235 ELASTIC STORE DELAY AFTER INITIALIZATION ........................................................................................................236 11.15 FRACTIONAL E1 SUPPORT (GAPPED CLOCK MODE) .................................................................................239 11.16 ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION (E1 MODE) ....................................................240 11.17 TRANSMIT HDLC CONTROLLER...............................................................................................................247 11.18 HDLC TRANSMIT EXAMPLE.....................................................................................................................255 11.19 INTERLEAVED PCM BUS OPERATION (IBO) .............................................................................................256 11.20 INTERFACING THE E1 TRANSMITTER TO THE BERT ..................................................................................258 11.21 E1 TRANSMIT SYNCHRONIZER.................................................................................................................260 12. BERT........................................................................................................................................262 BERT REGISTERS ..................................................................................................................................262 BERT DESCRIPTION AND OPERATION .....................................................................................................263 PATTERN GENERATION ...........................................................................................................................264 PATTERN SYNCHRONIZATION...................................................................................................................265 BER CALCULATION.................................................................................................................................265 ERROR GENERATION ..............................................................................................................................265 BERT CONTROL REGISTERS ..................................................................................................................267 BERT STATUS REGISTER .......................................................................................................................271 PSEUDORANDOM PATTERN REGISTERS ...................................................................................................272 COUNT REGISTERS .................................................................................................................................274 RAM ACCESS.........................................................................................................................................275 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 12.10 12.11 13. 13.1 13.2 13.3 13.4 13.5 FUNCTIONAL TIMING .............................................................................................................276 DELAYS ..................................................................................................................................................276 T1 RECEIVER FUNCTIONAL TIMING DIAGRAMS .........................................................................................277 T1 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS ...................................................................................282 E1 RECEIVER FUNCTIONAL TIMING DIAGRAMS .........................................................................................286 E1 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS ...................................................................................288 14. 15. 15.1 15.2 15.3 15.4 15.5 OPERATING PARAMETERS ...................................................................................................291 TIMING .....................................................................................................................................292 MICROPROCESSOR BUS AC CHARACTERISTICS .......................................................................................292 RECEIVER AC CHARACTERISTICS............................................................................................................295 TRANSMIT AC CHARACTERISTICS............................................................................................................298 JTAG INTERFACE TIMING .......................................................................................................................301 SYSTEM CLOCK AC CHARACTERISTICS ...................................................................................................301 16. 16.1 16.2 16.3 JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT...............................302 TAP CONTROLLER STATE MACHINE ........................................................................................................303 INSTRUCTION REGISTER..........................................................................................................................306 TEST REGISTERS....................................................................................................................................307 17. 18. 19. PACKAGE INFORMATION ......................................................................................................308 THERMAL INFORMATION ......................................................................................................309 REVISION HISTORY................................................................................................................309 4 DS26401 Octal T1/E1/J1 Framer LIST OF FIGURES Figure 3-1. Block Diagram ........................................................................................................................................10 Figure 3-2. Typical PLL Connection..........................................................................................................................11 Figure 3-3. Typical Bipolar Network-Side Interface to Framers................................................................................11 Figure 3-4. Typical NRZ Network-Side Interface to Framers....................................................................................12 Figure 7-1. Internal IBO Multiplexer Equivalent Circuit--4.096MHz .........................................................................28 Figure 7-2. Internal IBO Multiplexer Equivalent Circuit--8.192MHz .........................................................................29 Figure 7-3. Internal IBO Multiplexer Equivalent Circuit--16.394MHz ......................................................................30 Figure 8-1. RSYNC Input in H.100 (CT Bus) Mode ..................................................................................................50 Figure 8-2. TSSYNC Input in H.100 (CT Bus) Mode ................................................................................................51 Figure 8-3. Receive HDLC Example........................................................................................................................99 Figure 9-1. HDLC Message Transmit Example .....................................................................................................141 Figure 10-1. RSYNC Input in H.100 (CT Bus) Mode ..............................................................................................162 Figure 10-2. TSSYNC Input in H.100 (CT Bus) Mode ............................................................................................163 Figure 10-3. Receive HDLC Example....................................................................................................................207 Figure 11-1. HDLC Message Transmit Example ....................................................................................................255 Figure 12-1. Shared BERT Block Diagram .............................................................................................................266 Figure 13-1. T1 Receive-Side D4 Timing ...............................................................................................................277 Figure 13-2. T1 Receive-Side ESF Timing .............................................................................................................277 Figure 13-3. T1 Receive-Side Boundary Timing (Elastic Store Disabled) .............................................................278 Figure 13-4. T1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled)..............................................278 Figure 13-5. T1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled)..............................................279 Figure 13-6. T1 Receive-Side Interleave Bus Operation, BYTE Mode...................................................................280 Figure 13-7. T1 Receive-Side Interleave Bus Operation, FRAME Mode................................................................281 Figure 13-8. T1 Transmit-Side D4 Timing ..............................................................................................................282 Figure 13-9. T1 Transmit-Side ESF Timing ............................................................................................................282 Figure 13-10. T1 Transmit-Side Boundary Timing (Elastic Store Disabled) ...........................................................283 Figure 13-11. T1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled) ..........................................283 Figure 13-12. T1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled) ..........................................284 Figure 13-13. T1 Transmit-Side Interleave Bus Operation, BYTE Mode................................................................284 Figure 13-14. T1 Transmit Interleave Bus Operation, FRAME Mode.....................................................................285 Figure 13-15. E1 Receive-Side Timing ...................................................................................................................286 Figure 13-16. E1 Receive-Side Boundary Timing (Elastic Store Disabled) ............................................................286 Figure 13-17. E1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled) ...........................................287 Figure 13-18. E1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled) ...........................................287 Figure 13-19. E1 Transmit-Side Timing..................................................................................................................288 Figure 13-20. E1 Transmit-Side Boundary Timing (Elastic Store Disabled)...........................................................288 Figure 13-21. E1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled) .........................................289 Figure 13-22. E1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled) ..........................................289 Figure 13-23. E1 G.802 Timing...............................................................................................................................290 Figure 15-1. Intel Bus Read Timing (BTS = 0).......................................................................................................293 Figure 15-2. Intel Bus Write Timing (BTS = 0).......................................................................................................293 Figure 15-3. Motorola Bus Read Timing (BTS = 1) ...............................................................................................294 Figure 15-4. Motorola Bus Write Timing (BTS = 1) ...............................................................................................294 Figure 15-5. Receive Framer Timing--Backplane (T1 Mode)...............................................................................295 Figure 15-6. Receive-Side Timing--Elastic Store Enabled (T1 Mode)..................................................................296 Figure 15-7. Receive Framer Timing--Line Side ..................................................................................................297 Figure 15-8. Transmit Formatter Timing--Backplane ...........................................................................................299 Figure 15-9. Transmit Formatter Timing, Elastic Store Enabled ...........................................................................300 Figure 15-10. Transmit Formatter Timing--Line Side ...........................................................................................300 Figure 15-11. JTAG Interface Timing Diagram.......................................................................................................301 Figure 16-1. JTAG Functional Block Diagram ........................................................................................................302 Figure 16-2. Tap Controller State Diagram............................................................................................................303 5 DS26401 Octal T1/E1/J1 Framer LIST OF TABLES Table 7-1. Pin Functions with IBO Mux Enabled ......................................................................................................31 Table 8-1. T1 Alarm Criteria .....................................................................................................................................53 Table 8-2. T1 Line-Code Violation Counting Options ...............................................................................................66 Table 8-3. T1 Path-Code Violation Counting Arrangements ....................................................................................67 Table 8-4. T1 Frames Out-of-Sync Counting Arrangements ....................................................................................68 Table 10-1. E1 Sync/Resync Criteria ......................................................................................................................159 Table 10-2. E1 Alarm Criteria .................................................................................................................................165 Table 10-3. E1 Line Code Violation Counting Options ...........................................................................................177 Table 12-1. Pseudo-Random Pattern Generation ..................................................................................................273 Table 13-1. Throughput Delays ..............................................................................................................................276 Table 16-1. Instruction Codes for IEEE 1149.1 Architecture ..................................................................................306 Table 16-2. ID Code Structure ................................................................................................................................307 6 DS26401 Octal T1/E1/J1 Framer 1. APPLICABLE STANDARDS The DS26401 conforms to the applicable parts of the following standards. SPECIFICATION ANSI T1.102-1993 T1.107-1995 T1.231-1997 T1.403-1999 AT&T TR54016 TR62411 ITU G.704, 1995 G.706, 1991 G.732, 1993 G.736, 1993 G.775, 1994 G.823, 1993 I.431, 1993 O.151, 1992 O.161, 1988 ETSI ETS 300 011, 1998 ETS 300 166, 1993 ETS 300 233, 1994 CTR 4, 1995 I.432, 1993 CTR 12, 1993 CTR 13, 1996 TTC JT-G.704, 1995 JTI.431, 1995 Synchronous Frame Structures used at 1544, 6312, 2048, 8488, and 44,736 kbit/s Hierarchical Levels Frame Alignment and Cyclic Redundancy Check (CRC) Procedures Relating to Basic Frame Structures Defined in Recommendation G.704 Characteristics of Primary PCM Multiplex Equipment Operating at 2048 kbit/s Characteristics of a synchronous digital multiplex equipment operating at 2048 kbit/s Loss Of Signal (LOS) and Alarm Indication Signal (AIS) Defect Detection and Clearance Criteria The Control of Jitter and Wander Within Digital Networks Which are Based on the 2048kbps Hierarchy Primary Rate User-Network Interface--Layer 1 Specification Error Performance Measuring Equipment Operating at the Primary Rate and Above In-service code violation monitors for digital systems Integrated Services Digital Network (ISDN); Primary rate User-Network Interface (UNI); Part 1: Layer 1 specification Transmission and multiplexing; Physical/electrical characteristics of hierarchical digital interfaces for equipment using the 2048 kbit/s-based plesiochronous or synchronous digital hierarchies Integrated Services Digital Network (ISDN); Access digital section for ISDN primary rate Integrated Services Digital Network (ISDN); Attachment requirements for terminal equipment to connect to an ISDN using ISDN primary rate access B-ISDN User-Network Interface--Physical Layer Specification-ITU-T Business Telecommunications (BT); Open Network Provision (ONP) technical requirements; 2048 kbit/s digital unstructured leased lines (D2048U) attachment requirements for terminal equipment interface Business Telecommunications (BTC); 2048 kbit/s digital structured leased lines (D2048S); Attachment requirements for terminal equipment interface Frame Structures on Primary and Secondary Hierarchical Digital Interfaces ISDN Primary Rate User-Network Interface Layer 1 Specification TITLE Digital Hierarchy--Electrical Interfaces Digital Hierarchy--Formats Specification Digital Hierarchy--Layer 1 In-Service Digital Transmission Performance Monitoring Network and Customer Installation Interfaces--DS1 Electrical Interface Requirements for Interfacing Digital Terminal Equipment to Services Employing the Extended Superframe Format High Capacity Digital Service Channel Interface Specification 7 DS26401 Octal T1/E1/J1 Framer 2. FEATURES 2.1 Framer/Formatter Fully Independent Transmit and Receive Functionality Full Receive and Transmit Path Transparency T1 Framing Formats D4 and ESF per T1.403, and Expanded SLC-96 Support (TR-TSY-008) E1 FAS Framing and CRC-4 Multiframe per G.704/G.706 and G.732 CAS Multiframe Detailed Alarm and Status Reporting with Optional Interrupt Support Large Path and Line Error Counters for T1: BPV, CV, CRC6, and Framing Bit Errors E1: BPV, CV, CRC4, E-Bit, and Frame Alignment Errors Timed or Manual Update Modes DS1 Idle Code Generation on a Per-Channel Basis in Both Transmit and Receive Paths User-Defined Digital Milliwatt ANSI T1.403-1998 Support G.965 V5.2 Link Detect Ability to Monitor One DS0 Channel in Both the Transmit and Receive Paths In-Band Repeating Pattern Generators and Detectors Three Independent Detectors Patterns from 1 to 8 bits or 16 bits in Length Bit Oriented Code (BOC) Support Flexible Signaling Support Software- or Hardware-Based Interrupt Generated on Change of Signaling Data Signaling Debounce Optional Receive Signaling Freeze on Loss of Frame (LOF), Loss of Signal (LOS), or Change-of-Frame Alignment Hardware Pins Provided to Indicate Loss of Frame, Loss of Signal, Loss-of-Transmit Clock (LOTC), or Signaling Freeze Condition Automatic RAI Generation to ETS 300 011 Specifications RAI-CI and AIS-CI Support Expanded Access to Sa and Si Bits Option to Extend Carrier Loss Criteria to a 1ms Period as per ETS 300 233 Japanese J1 Support Ability to Calculate and Check CRC6 According to the Japanese Standard Ability to Generate Yellow Alarm According to the Japanese Standard 2.2 System Interface Independent Two-Frame Receive and Transmit Elastic Stores Independent Control and Clocking Controlled Slip Capability with Status Minimum Delay Mode Supported Maximum Backplane Rate of 16.384MHz in IBO Mode Supports T1 to E1 Conversion Programmable Output Clocks for Fractional T1, E1, H0, and H12 Applications Interleaving PCM Bus Operation (IBO) Hardware Signaling Capability Receive Signaling Reinsertion to a Backplane Multiframe Sync Availability of Signaling in a Separate PCM Data Stream Signaling Freezing Ability to Pass the T1 F-Bit Position Through the Elastic Stores in the 2.048MHz Backplane Mode User-Selectable Synthesized Clock Output 8 DS26401 Octal T1/E1/J1 Framer 2.3 HDLC Controllers HDLC Engine (One per Framer): Independent 64-byte Rx and Tx Buffers with Interrupt Support Access FDL, Sa, or Single DS0 Channel Compatible with Polled or Interrupt Driven Environments 2.4 Test and Diagnostics Global, Full-Feature BERT 32 Any Pseudo-Random Pattern Up to 2 - 1 Up to 32 Taps can be Used Simultaneously User-Defined Repetitive Patterns Up to 512 Bytes in Length Large, 48-Bit Error and Bit Counters Map to Any Framer/DS0/FDL (T1) or Sa Bits (E1) Programmable Error Insertion BPV Insertion F-Bit Corruption for Line Testing Loopbacks Remote Local Per-Channel IEEE 1149.1 Support 2.5 Control Port 8-Bit Parallel Control Port Intel or Motorola Nonmultiplexed Support Flexible Status Registers Support Polled, Interrupt, or Hybrid Program Environments Software Reset Supported Hardware Reset Pin 9 DS26401 Octal T1/E1/J1 Framer 3. BLOCK DIAGRAMS Figure 3-1. Block Diagram DS26401 FRAMER #8 FRAMER #7 FRAMER #6 FRAMER #5 BERT THE BERT FUNCTION MAY BE ASSIGNED TO ANY PORT RPOS RNEG RCLK TPOS TNEG TCLKO BACKPLANE T1/E1 BACKPLANE INTERFACE T1/E1 BACKPLANE INTERFACE FRAMER T1/E1 FRAMER #3 BACKPLANE INTERFACE FRAMER T1/E1 RECEIVE AND ELASTIC BACKPLANE FRAMERFRAMER #2 INTERFACE T1/E1 ELASTIC IBO TRANSMIT BACKPLANE STORES INTERFACE FRAMER T1/E1 HDLCs BACKPLANE ELASTIC BACKPLANE INTERFACE FRAMER T1/E1 HDLCs BACKPLANE STORES ELASTIC STORES INTERFACE FRAMER T1/E1 HDLCs SIGNALS ELASTIC STORES INTERFACE FRAMER ELASTIC HDLCs STORES FRAMER ELASTIC HDLCs STORES ELASTIC HDLCs STORES THE IBO FUNCTION ALLOWS HDLCs STORES ACCESS TO ALL 8 PORTS HDLCs INDIVIDUALLY OR AS 4 GROUPS FRAMER #4 OF 2, 2 GROUPS OF 4, OR 1 GROUP OF 8 PORTS. MICRO PROCESSOR INTERFACE JTAG PORT PLL CONTROLLER PORT TEST PORT CLOCKS 10 DS26401 Octal T1/E1/J1 Framer Figure 3-2. Typical PLL Connection DS26401 GCLK_IN 2.048MHz or 1.544MHz REF_CLK GCLK_OUT PLL BPCLK 2.048MHz, 4.096MHz 8.192MHz or 16.384MHz Figure 3-3. Typical Bipolar Network-Side Interface to Framers DS26401 RPOSx T1/E1 LIU OR OTHER SOURCE OF BIPOLAR DATA RNEGx RCLKx TPOSx TNEGx TCLKx 1 OF 8 FRAMERS 2.048MHz or 1.544MHz 11 DS26401 Octal T1/E1/J1 Framer Figure 3-4. Typical NRZ Network-Side Interface to Framers DS26401 RPOSx T1/E1 LIU OR OTHER SOURCE OF NRZ DATA RNEGx RCLKx TPOSx TNEGx TCLKx 1 OF 8 FRAMERS 2.048MHz or 1.544MHz NOTE: SET TCR3.7 = 1 TO SELECT NRZ MODE FOR TPOSx. SET RCR3.6 = 1 TO SELECT NRZ MODE FOR RPOSx. 12 DS26401 Octal T1/E1/J1 Framer 4. SIGNAL LIST (SORTED BY SIGNAL NAME) PIN B5 A5 C6 E8 A6 B6 D7 C7 A7 D8 C8 A8 F16 B2 B4 A1 C4 A2 B3 D5 A3 D6 A4 G16 G13 R12 E9 N10 T11 P11 T10 R11 B7, B13, D2, D15, E6, E14, F2, G14, J16, M9, N15, P2, P8, R5 B1 H1 L5 P6 N11 M15 E15 A13 C2 H4 L4 N6 M11 L14 E16 C12 E7 F15 T12 E5 H3 N1 T5 T13 NAME ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 BPCLK BTS CS DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 GCLK_IN GCLK_OUT HIZE INT JTCLK JTDI JTDO JTMS JTRST N.C. RCHBLK/CLK1 RCHBLK/CLK2 RCHBLK/CLK3 RCHBLK/CLK4 RCHBLK/CLK5 RCHBLK/CLK6 RCHBLK/CLK7 RCHBLK/CLK8 RCLK1 RCLK2 RCLK3 RCLK4 RCLK5 RCLK6 RCLK7 RCLK8 RD (DS) REF_CLK RESET RF/RMSYNC1 RF/RMSYNC2 RF/RMSYNC3 RF/RMSYNC4 RF/RMSYNC5 TYPE I I I I I I I I I I I I O I I I/O I/O I/O I/O I/O I/O I/O I/O I O I O I I O I I FUNCTION mP Address Bus Bit 0 mP Address Bus Bit 1 mP Address Bus Bit 2 mP Address Bus Bit 3 mP Address Bus Bit 4 mP Address Bus Bit 5 mP Address Bus Bit 6 mP Address Bus Bit 7 mP Address Bus Bit 8 mP Address Bus Bit 9 mP Address Bus Bit 10 mP Address Bus Bit 11 Programmable Backplane Clock Motorola or Intel Bus Type Select Chip Select (Active Low) mP Data Bus Bit 0 mP Data Bus Bit 1 mP Data Bus Bit 2 mP Data Bus Bit 3 mP Data Bus Bit 4 mP Data Bus Bit 5 mP Data Bus Bit 6 mP Data Bus Bit 7 Global Clock Input Global Clock Output High-Z Enable Interrupt (Active Low) JTAG Clock JTAG Data Input JTAG Data Output JTAG Test Mode Select JTAG Reset No Connect O O O O O O O O I I I I I I I I I I I O O O O O Rx Channel Block/Clock for Framer 1 Rx Channel Block/Clock for Framer 2 Rx Channel Block/Clock for Framer 3 Rx Channel Block/Clock for Framer 4 Rx Channel Block/Clock for Framer 5 Rx Channel Block/Clock for Framer 6 Rx Channel Block/Clock for Framer 7 Rx Channel Block/Clock for Framer 8 Rx Clock for Framer 1 Rx Clock for Framer 2 Rx Clock for Framer 3 Rx Clock for Framer 4 Rx Clock for Framer 5 Rx Clock for Framer 6 Rx Clock for Framer 7 Rx Clock for Framer 8 Read Strobe (Active Low) Reference Clock (1.544MHz/2.048MHz) Global Reset (Active Low) Rx Frame/MF Sync for Framer 1 Rx Frame/MF Sync for Framer 2 Rx Frame/MF Sync for Framer 3 Rx Frame/MF Sync for Framer 4 Rx Frame/MF Sync for Framer 5 13 DS26401 Octal T1/E1/J1 Framer PIN M16 F14 C13 D1 K2 T1 P7 P13 K14 C15 D11 F5 J4 R2 T7 T16 K13 C16 A11 C1 H5 M4 R6 N12 L16 D16 B12 D4 J2 P1 T6 T14 L13 G12 E11 E4 J1 R1 M7 R14 L15 F12 A12 D3 J3 N3 N7 T15 K12 F13 C11 E3 K1 M5 R7 R15 K16 E13 B11 C3 H2 N2 M6 R13 NAME RF/RMSYNC6 RF/RMSYNC7 RF/RMSYNC8 RLOF/LOTC1 RLOF/LOTC2 RLOF/LOTC3 RLOF/LOTC4 RLOF/LOTC5 RLOF/LOTC6 RLOF/LOTC7 RLOF/LOTC8 RLOS/RSIGF1 RLOS/RSIGF2 RLOS/RSIGF3 RLOS/RSIGF4 RLOS/RSIGF5 RLOS/RSIGF6 RLOS/RSIGF7 RLOS/RSIGF8 RNEG1 RNEG2 RNEG3 RNEG4 RNEG5 RNEG6 RNEG7 RNEG8 RPOS1 RPOS2 RPOS3 RPOS4 RPOS5 RPOS6 RPOS7 RPOS8 RSER1 RSER2 RSER3 RSER4 RSER5 RSER6 RSER7 RSER8 RSIG1 RSIG2 RSIG3 RSIG4 RSIG5 RSIG6 RSIG7 RSIG8 RSYNC1 RSYNC2 RSYNC3 RSYNC4 RSYNC5 RSYNC6 RSYNC7 RSYNC8 RSYSCLK1 RSYSCLK2 RSYSCLK3 RSYSCLK4 RSYSCLK5 TYPE O O O O O O O O O O O O O O O O O O O I I I I I I I I I I I I I I I I O O O O O O O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I FUNCTION Rx Frame/MF Sync for Framer 6 Rx Frame/MF Sync for Framer 7 Rx Frame/MF Sync for Framer 8 RLOF or LOTC for Framer 1 RLOF or LOTC for Framer 2 RLOF or LOTC for Framer 3 RLOF or LOTC for Framer 4 RLOF or LOTC for Framer 5 RLOF or LOTC for Framer 6 RLOF or LOTC for Framer 7 RLOF or LOTC for Framer 8 RLOS for Framer 1 RLOS for Framer 2 RLOS for Framer 3 RLOS for Framer 4 RLOS for Framer 5 RLOS for Framer 6 RLOS for Framer 7 RLOS for Framer 8 Rx Negative Data for Framer 1 Rx Negative Data for Framer 2 Rx Negative Data for Framer 3 Rx Negative Data for Framer 4 Rx Negative Data for Framer 5 Rx Negative Data for Framer 6 Rx Negative Data for Framer 7 Rx Negative Data for Framer 8 Rx Positive Data for Framer 1 Rx Positive Data for Framer 2 Rx Positive Data for Framer 3 Rx Positive Data for Framer 4 Rx Positive Data for Framer 5 Rx Positive Data for Framer 6 Rx Positive Data for Framer 7 Rx Positive Data for Framer 8 Receive Serial Data for Framer 1 Receive Serial Data for Framer 2 Receive Serial Data for Framer 3 Receive Serial Data for Framer 4 Receive Serial Data for Framer 5 Receive Serial Data for Framer 6 Receive Serial Data for Framer 7 Receive Serial Data for Framer 8 Receive Signaling Data for Framer 1 Receive Signaling Data for Framer 2 Receive Signaling Data for Framer 3 Receive Signaling Data for Framer 4 Receive Signaling Data for Framer 5 Receive Signaling Data for Framer 6 Receive Signaling Data for Framer 7 Receive Signaling Data for Framer 8 Rx Frame/MF Sync for Framer 1 Rx Frame/MF Sync for Framer 2 Rx Frame/MF Sync for Framer 3 Rx Frame/MF Sync for Framer 4 Rx Frame/MF Sync for Framer 5 Rx Frame/MF Sync for Framer 6 Rx Frame/MF Sync for Framer 7 Rx Frame/MF Sync for Framer 8 Receive System Clock for Framer 1 Receive System Clock for Framer 2 Receive System Clock for Framer 3 Receive System Clock for Framer 4 Receive System Clock for Framer 5 14 DS26401 Octal T1/E1/J1 Framer PIN L12 H12 D12 F3 L2 R3 N8 P14 J15 A16 C10 F4 L1 T3 R9 P15 J13 B15 B10 G1 M3 P5 P10 M14 H13 D13 B8 P12 M10 G5 L3 P4 T9 P16 H15 A15 B9 F1 J5 N4 M8 N13 J12 E12 A10 G4 M1 N5 P9 N14 H16 B14 C9 G3 M2 T4 R10 M13 H14 C14 A9 E1 K4 T2 NAME RSYSCLK6 RSYSCLK7 RSYSCLK8 TCHBLK/CLK1 TCHBLK/CLK2 TCHBLK/CLK3 TCHBLK/CLK4 TCHBLK/CLK5 TCHBLK/CLK6 TCHBLK/CLK7 TCHBLK/CLK8 TCLK1 TCLK2 TCLK3 TCLK4 TCLK5 TCLK6 TCLK7 TCLK8 TCLKO1 TCLKO2 TCLKO3 TCLKO4 TCLKO5 TCLKO6 TCLKO7 TCLKO8 TESTPIN1 TESTPIN2 TNEG1 TNEG2 TNEG3 TNEG4 TNEG5 TNEG6 TNEG7 TNEG8 TPOS1 TPOS2 TPOS3 TPOS4 TPOS5 TPOS6 TPOS7 TPOS8 TSER1 TSER2 TSER3 TSER4 TSER5 TSER6 TSER7 TSER8 TSIG1 TSIG2 TSIG3 TSIG4 TSIG5 TSIG6 TSIG7 TSIG8 TSSYNC1 TSSYNC2 TSSYNC3 TYPE I I I O O O O O O O O I I I I I I I I O O O O O O O O I I O O O O O O O O O O O O O O O O I I I I I I I I I I I I I I I I I I I FUNCTION Receive System Clock for Framer 6 Receive System Clock for Framer 7 Receive System Clock for Framer 8 Tx Channel Block/Clock for Framer 1 Tx Channel Block/Clock for Framer 2 Tx Channel Block/Clock for Framer 3 Tx Channel Block/Clock for Framer 4 Tx Channel Block/Clock for Framer 5 Tx Channel Block/Clock for Framer 6 Tx Channel Block/Clock for Framer 7 Tx Channel Block/Clock for Framer 8 Tx Clock for Framer 1 Tx Clock for Framer 2 Tx Clock for Framer 3 Tx Clock for Framer 4 Tx Clock for Framer 5 Tx Clock for Framer 6 Tx Clock for Framer 7 Tx Clock for Framer 8 Tx Clock Output for Framer 1 Tx Clock Output for Framer 2 Tx Clock Output for Framer 3 Tx Clock Output for Framer 4 Tx Clock Output for Framer 5 Tx Clock Output for Framer 6 Tx Clock Output for Framer 7 Tx Clock Output for Framer 8 Used for factory tests (Note 1) Used for factory tests (Note 1) Tx Negative Data for Framer 1 Tx Negative Data for Framer 2 Tx Negative Data for Framer 3 Tx Negative Data for Framer 4 Tx Negative Data for Framer 5 Tx Negative Data for Framer 6 Tx Negative Data for Framer 7 Tx Negative Data for Framer 8 Tx Positive Data for Framer 1 Tx Positive Data for Framer 2 Tx Positive Data for Framer 3 Tx Positive Data for Framer 4 Tx Positive Data for Framer 5 Tx Positive Data for Framer 6 Tx Positive Data for Framer 7 Tx Positive Data for Framer 8 Transmit Serial Data for Framer 1 Transmit Serial Data for Framer 2 Transmit Serial Data for Framer 3 Transmit Serial Data for Framer 4 Transmit Serial Data for Framer 5 Transmit Serial Data for Framer 6 Transmit Serial Data for Framer 7 Transmit Serial Data for Framer 8 Transmit Signaling Data for Framer 1 Transmit Signaling Data for Framer 2 Transmit Signaling Data for Framer 3 Transmit Signaling Data for Framer 4 Transmit Signaling Data for Framer 5 Transmit Signaling Data for Framer 6 Transmit Signaling Data for Framer 7 Transmit Signaling Data for Framer 8 Transmit System Sync for Framer 1 Transmit System Sync for Framer 2 Transmit System Sync for Framer 3 15 DS26401 Octal T1/E1/J1 Framer PIN T8 R16 J14 D14 D10 G2 K5 R4 N9 N16 G15 A14 D9 E2 K3 P3 R8 M12 K15 B16 E10 F8, F9, G8, G9, H6, H7 H10, H11, J6, J7, J10, J11, K8, K9, L8, L9 F6, F7, F10, F11, G6, G7, G10, G11, H8, H9, J8, J9, K6, K7, K10, K11, L6, L7, L10, L11 C5 Note 1: Connect to VSS. NAME TSSYNC4 TSSYNC5 TSSYNC6 TSSYNC7 TSSYNC8 TSYNC1 TSYNC2 TSYNC3 TSYNC4 TSYNC5 TSYNC6 TSYNC7 TSYNC8 TSYSCLK1 TSYSCLK2 TSYSCLK3 TSYSCLK4 TSYSCLK5 TSYSCLK6 TSYSCLK7 TSYSCLK8 VDD TYPE I I I I I I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I -- FUNCTION Transmit System Sync for Framer 4 Transmit System Sync for Framer 5 Transmit System Sync for Framer 6 Transmit System Sync for Framer 7 Transmit System Sync for Framer 8 Tx Frame/MF Sync for Framer 1 Tx Frame/MF Sync for Framer 2 Tx Frame/MF Sync for Framer 3 Tx Frame/MF Sync for Framer 4 Tx Frame/MF Sync for Framer 5 Tx Frame/MF Sync for Framer 6 Tx Frame/MF Sync for Framer 7 Tx Frame/MF Sync for Framer 8 Transmit System Clock for Framer 1 Transmit System Clock for Framer 2 Transmit System Clock for Framer 3 Transmit System Clock for Framer 4 Transmit System Clock for Framer 5 Transmit System Clock for Framer 6 Transmit System Clock for Framer 7 Transmit System Clock for Framer 8 VSS WR (R/W) -- I Signal Write Strobe (Active Low) 16 DS26401 Octal T1/E1/J1 Framer 5. SIGNAL DESCRIPTIONS 5.1 Receive Framer Signals Signal Name: RPOS (1-8) Signal Description: Receive Positive Data Input Signal Type: Input Sampled on the falling edge of RCLK for bipolar data to be clocked through the receive side framer. Data on RPOS and RNEG will typically be AMI, B8ZS, or HDB3 format bipolar data. RPOS can be used for unipolar (NRZ) data if enabled by the Input Data Format bit (IDF) at RCR3.7. Signal Name: RNEG (1-8) Signal Description: Receive Negative Data Input Signal Type: Input Sampled on the falling edge of RCLK for bipolar data to be clocked through the receive side framer. Data on RPOS and RNEG will typically be AMI, B8ZS, or HDB3 format bipolar data. The RNEG input should be grounded when the DS26401 is set to receive unipolar (NRZ) data, enabled by the Input Data Format bit (IDF) at RCR3.7. Signal Name: RCLK (1-8) Signal Description: Receive Clock Signal Type: Input A 1.544MHz (T1) or 2.048MHz (E1) clock that is used to clock data through the receive side framer. Signal Name: RSER (1-8) Signal Description: Receive Serial Data Signal Type: Output Received NRZ serial data. Updated on rising edges of RCLK when the receive side elastic store is disabled. Updated on the rising edges of RSYSCLK when the receive side elastic store is enabled. Signal Name: RSIG (1-8) Signal Description: Receive Signaling Output Signal Type: Output Outputs signaling bits in a PCM format. Updated on rising edges of RCLK when the receive side elastic store is disabled. Updated on the rising edges of RSYSCLK when the receive side elastic store is enabled. Signal Name: RSYNC (1-8) Signal Description: Receive Sync Signal Type: Input/Output An extracted pulse, one RCLK wide that identifies either frame or multiframe boundaries. If set to output frame boundaries then RSYNC can be programmed to output doublewide pulses on signaling frames in T1 mode. Signal Name: RSYSCLK (1-8) Signal Description: Receive System Clock Signal Type: Input 1.544MHz, 2.048MHz, 4.096MHz, or 8.192MHz, or 16.384MHz receive backplane clock. Only used when the receive-side elastic store function is enabled. Should be tied low in applications that do not use the receive-side elastic store. 17 DS26401 Octal T1/E1/J1 Framer Signal Name: RCHBLK/CLK (1-8) Signal Description: Receive Channel Block/Clock Signal Type: Output Pin can be configured to output either RCHBLK or RCHCLK. RCHBLK is a user programmable output that can be forced high or low during any of the 24 T1 or 32 E1 channels. Synchronous with RCLK when the receive side elastic store is disabled. Synchronous with RSYSCLK when the receive-side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD controller in applications where not all channels are used such as fractional service, 384kbps, service, 768kbps, or ISDN-PRI. Also useful for locating individual channels in drop-and-insert applications, for external per-channel loopback, and for per-channel conditioning. RCHCLK is a 192 kHz (T1) or 256kHz (E1) clock that pulses high during the LSB of each channel. Can also be programmed to output a gated bit clock useful for fractional services. Synchronous with RCLK when the receive side elastic store is disabled. Synchronous with RSYSCLK when the receive side elastic store is enabled. Useful for parallel-to-serial conversion of channel data. Signal Name: RLOF/LOTC (1-8) Signal Description: Receive Loss of Frame/Loss of Transmit Clock Signal Type: Output A dual function output that is controlled by the GCR1.5 control bit. This pin can be programmed to either toggle high when the synchronizer is searching for the frame and multiframe or to toggle high if the TCLK pin has not been toggled for approximately three clock periods. Signal Name: RLOS/RSIGF (1-8) Signal Description: Receive Loss of Signal/Receive Signaling Freeze Signal Type: Output A dual function output that is controlled by the GCR2.3 control bit. This pin can be programmed to toggle high when the framer detects a loss of signal condition, or when the signaling data is frozen via either automatic or manual intervention. Used to alert downstream equipment of the condition. Signal Name: RF/RMSYNC (1-8) Signal Description: Receive Frame Sync/Receive Multiframe Sync Signal Type: Output A dual function output controlled by the GCR2.2 control bit. RFSYNC is an extracted 8kHz pulse, one RCLK wide that identifies frame boundaries. RMSYNC is an extracted pulse, one RCLK wide (elastic store disabled) or one RSYSCLK wide (elastic store enabled), which identifies multiframe boundaries. When the receive elastic store is enabled, the RMSYNC signal indicates the multiframe sync on the system (backplane) side of the e-store. In E1 mode, will indicate either the CRC4 or CAS multiframe as determined by the RSMS2 control bit at RIOCR.1 18 DS26401 Octal T1/E1/J1 Framer 5.2 Transmit Framer Signals Signal Name: TPOS (1-8) Signal Description: Transmit Positive Data Output Signal Type: Output Update on the rising edge of TCLK with the bipolar data out of the transmit side formatter. Can be programmed to source NRZ data via the output data format (TCR3.7) control bit. Signal Name: TNEG (1-8) Signal Description: Transmit Negative Data Output Signal Type: Output Update on the rising edge of TCLK with the bipolar data out of the transmit side formatter. Signal Name: TCLK (1-8) Signal Description: Transmit Clock Signal Type: Input A 1.544MHz or a 2.048MHz primary clock. Used to clock data through the transmit side formatter. Signal Name: TCLKO (1-8) Signal Description: Transmit Clock Output Signal Type: Output This clock is provided to simplify interface to a line interface unit (LIU). This signal is used to register the TPOS and TNEG outputs and is typically synchronous with the TCLK input. However, in framer and payload loopback applications this signal becomes synchronous with RCLK. Signal Name: TSER (1-8) Signal Description: Transmit Serial Data Signal Type: Input Transmit NRZ serial data. Sampled on the falling edge of TCLK when the transmit-side elastic store is disabled. Sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled. Signal Name: TSIG (1-8) Signal Description: Transmit Signaling Input Signal Type: Input When enabled, this input will sample signaling bits for insertion into outgoing PCM data stream. Sampled on the falling edge of TCLK when the transmit-side elastic store is disabled. Sampled on the falling edge of TSYSCLK when the transmit-side elastic store is enabled. Signal Name: TSYNC (1-8) Signal Description: Transmit Sync Signal Type: Input / Output A pulse at this pin will establish either frame or multiframe boundaries for the transmit side. This signal can also be programmed to output either a frame or multiframe pulse. If this pin is set to output pulses at frame boundaries, it can also be set to output doublewide pulses at signaling frames in T1 mode. Signal Name: TSSYNC (1-8) Signal Description: Transmit System Sync Signal Type: Input Only used when the transmit-side elastic store is enabled. A pulse at this pin will establish either frame or multiframe boundaries for the transmit side. Should be tied low in applications that do not use the transmit-side elastic store. 19 DS26401 Octal T1/E1/J1 Framer Signal Name: TSYSCLK (1-8) Signal Description: Transmit System Clock Signal Type: Input 1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz clock. Only used when the transmit-side elastic store function is enabled. Should be tied low in applications that do not use the transmit-side elastic store. Signal Name: TCHBLK/CLK (1-8) Signal Description: Transmit Channel Block Signal Type: Output A dual function pin. TCHBLK is a user programmable output that can be forced high or low during any of the channels. Synchronous with TCLK when the transmit side elastic store is disabled. Synchronous with TSYSCLK when the transmit side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD controller in applications where not all channels are used such as Fractional T1, Fractional E1, 384kbps (H0), 768kbps, or ISDN-PRI. Also useful for locating individual channels in drop-and-insert applications, for external per-channel loopback, and for per-channel conditioning. TCHCLK is a 192kHz (T1) or 256kHz (E1) clock that pulses high during the LSB of each channel. Can also be programmed to output a gated bit clock useful for fractional services. Synchronous with TCLK when the transmitside elastic store is disabled. Synchronous with TSYSCLK when the transmit-side elastic store is enabled. Useful for parallel-to-serial conversion of channel data. 5.3 Parallel Control Port Signal Name: ADDR[11:0] Signal Description: Microprocessor Address Bus Signal Type: Input This bus selects a specific register in the DS26401 during read/write access. ADDR11 is the MSB and ADDR0 is the LSB. Signal Name: DATA[7:0] Signal Description: Microprocessor Data Bus Signal Type: Input/Output This 8-bit, bidirectional data bus is used for read/write access of the DS26401 information and control registers. DATA7 is the MSB and DATA0 is the LSB. Signal Name: CS Signal Description: Chip Select Signal Type: Input This active-low signal is used to qualify register read/write accesses. The RD and WR signals are qualified with CS. Signal Name: RD (DS) Signal Description: Read Enable Signal Type: Input This active-low signal along with CS qualifies read access to one of the DS26401 registers. The DS26401 drives the DATA bus with the contents of the addressed register while RD and CS are both low. Signal Name: WR (R/W) Signal Description: Write Enable Signal Type: Input This active-low signal along with CS qualifies write access to one of the DS26401 registers. Data at DATA[7:0] is written into the addressed register at the rising edge of WR while CS is low. Signal Name: INT Signal Description: Interrupt Signal Type: Output This active-low, open-drain output is asserted when an unmasked interrupt event is detected. INT is deasserted when all interrupts have been acknowledged and serviced. 20 DS26401 Octal T1/E1/J1 Framer Signal Name: BTS Signal Description: Bus Type Select Signal Type: Input Set high to select Motorola bus timing, low to select Intel bus timing. This pin controls the function of the RD (DS), and WR (R/W) pins. If BTS = 1, these pins assume the function listed in parentheses (). 5.4 System Interface Signal Name: REF_CLK Signal Description: Reference Clock Signal Type: Input A continuous T1 (1.544MHz) or E1 (2.048MHz) clock used to create GCLK_OUT and BPCLK. Signal Name: GCLK_OUT Signal Description: Global Clock Output Signal Type: Output This output clock is generated from the REF_CLK input and is a 45MHz clock. This pin is usually connected to GCLK_IN. Signal Name: GCLK_IN Signal Description: Global Clock Input Signal Type: Input Primary clock for internal state machines. Can be connected to GCLK_OUT, or provided by the user. The GCLK_IN frequency must be between 43MHz and 49MHz for proper operation. Signal Name: BPCLK Signal Description: Backplane Clock Signal Type: Output Programmable clock output created from REFCLK. Can be set to 2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz. Signal Name: RESET Signal Description: System Reset Signal Type: Input Active-low reset. Forcing this input low sets all internal registers to their default value. Signal Name: HIZE Signal Description: High-Z Enable Signal Type: Input Active high. Forcing this input high when the RESET and JTRST pins are low will hold all outputs in high-impedance mode. 21 DS26401 Octal T1/E1/J1 Framer 5.5 Test Signal Name: JTRST Signal Description: IEEE 1149.1 Test Reset Signal Type: Input JTRST is used to asynchronously reset the test access port controller. After power-up, JTRST must be toggled from low to high. This action will set the device into the JTAG DEVICE ID mode. Pulling JTRST low restores normal device operation. JTRST is pulled high internally through a 10kW resistor operation. If boundary scan is not used, this pin should be held low. Signal Name: JTMS Signal Description: IEEE 1149.1 Test Mode Select Signal Type: Input This pin is sampled on the rising edge of JTCLK and is used to place the test access port into the various defined IEEE 1149.1 states. This pin has a 10kW pullup resistor. Signal Name: JTCLK Signal Description: IEEE 1149.1 Test Clock Signal Signal Type: Input This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge. Signal Name: JTDI Signal Description: IEEE 1149.1 Test Data Input Signal Type: Input Test instructions and data are clocked into this pin on the rising edge of JTCLK. This pin has a 10kW pullup resistor. Signal Name: JTDO Signal Description: IEEE 1149.1 Test Data Output Signal Type: Output Test instructions and data are clocked out of this pin on the falling edge of JTCLK. If not used, this pin should be left unconnected. 22 DS26401 Octal T1/E1/J1 Framer 6. REGISTER MAP The DS26401 has an 8-bit mP control bus with 12 address bits. The address bits are structured as follows: MSB LSB XXXXXXXXXXXX Per Port Registers (See below for exceptions) Rx/Tx Select: 0 Receive 1 Transmit Port Select: 000 Port 1 111 Port 8 23 DS26401 Octal T1/E1/J1 Framer 7. GLOBAL FUNCTIONS 7.1 Global Registers ADDRESS 0F0 0F1 0F2 0F3 0F4 0F5 0F6 0F7 0F8 0F9 0FA 0FB 0FC 0FD 0FE 0FF NAME GCR1 GCR2 -- -- -- -- -- -- IDR GSR1 GSR2 -- -- -- -- -- TYPE R/W R/W -- -- -- -- -- -- R R R -- -- -- -- -- FUNCTION Global Control Register 1 Global Control Register 2 Unused, must be set = 0 for proper operation Unused, must be set = 0 for proper operation Unused, must be set = 0 for proper operation Unused, must be set = 0 for proper operation Unused, must be set = 0 for proper operation Unused, must be set = 0 for proper operation Device ID Register Global Status Register 1 Global Status Register 2 Unused, must be set = 0 for proper operation Unused, must be set = 0 for proper operation Unused, must be set = 0 for proper operation Unused, must be set = 0 for proper operation Unused, must be set = 0 for proper operation PAGE 25 26 -- -- -- -- -- -- 35 36 37 -- -- -- -- -- 24 DS26401 Octal T1/E1/J1 Framer 7.2 Global Register Description and Operation Register Name: Register Description: Register Address: Bit # Name Default 7 BBEDIM 0 GCR1 Global Control Register 1 0F0h 6 BLOSIM 0 5 RLOFLTS 0 4 GIBO 0 3 REFCLKS 0 2 BWE 0 1 GCLE 0 0 GIPI 0 Bit 0 / Global Interrupt Pin Inhibit (GIPI) 0 = Normal operation (interrupt pin (INT) toggles low on an unmasked interrupt condition) 1 = Interrupt inhibit (interrupt pin (INT) is forced high (inactive) when this bit is set) Bit 1 / Global Counter Latch Enable (GCLE). A low-to-high transition on this bit, when enabled, latches the framer performance-monitor counters and the internal BERT counters. Each framer can be independently enabled to accept this input, as well as the BERT. This bit must be cleared and set again to perform another counter latch. Bit 2 / Bulk Write Enable (BWE). When this bit is set, a port write to one of the octal ports is mapped into all 8 ports. This bit is useful for device initialization. It must be cleared before performing a read operation. 0 = Normal operation 1 = Bulk write is enabled Bit 3 / Reference Clock-Frequency Select (REFCLKS). This bit sets the divider ratio of the internal clock generator depending on the frequency of the reference clock input. 0 = REF_CLK is 1.544MHz 1 = REF_CLK is 2.048MHz Bit 4 / Ganged IBO Enable (GIBO). This bit is used to select either the internal mux for IBO operation or externally wire-OR operation. Normally this bit should be set = 0 and the internal mux is used. 0 = Use internal IBO mux 1 = Externally wire-OR TSERs and RSERs for IBO operation Bit 5 / Receive Loss-of-Frame/Loss-of-Transmit Clock-Indication Select (RLOFLTS) 0 = RLOF/LOTCx pins indicate receive loss-of-frame 1 = RLOF/LOTCx pins indicate loss-of-transmit clock Bit 6 / BERT Loss-of-Sync Interrupt Mask (BLOSIM) 0 = DS26401 does not generate an interrupt on INT for a BERT LOS 1 = DS26401 generates an interrupt on INT for a BERT LOS Bit 7 / BERT Bit-Error-Detect Interrupt Mask (BBEDIM) 0 = DS26401 does not generate an interrupt on INT for a BERT bit-error detect 1 = DS26401 generates an interrupt on INT for a BERT bit-error detect 25 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 IBOMS1 0 GCR2 Global Control Register 2 0F1h 6 IBOMS0 0 5 BPCLK1 0 4 BPCLK0 0 3 RLOSSFS 0 2 RFMSS 0 1 TCBCS 0 0 RCBCS 0 Bit 0 / Receive-Channel Block/Clock Select (RCBCS). This bit controls the function of all eight RCHBLK/CLK pins. 0 = RCHBLK/CLK pins output RCHBLK (1-8) (receive-channel block) 1 = RCHBLK/CLK pins output RCHCLK (1-8) (receive-channel clock) Bit 1 / Transmit-Channel Block/Clock Select (TCBCS). This bit controls the function of all eight TCHBLK/CLK pins. 0 = TCHBLK/CLK pins output TCHBLK (1-8) (transmit-channel block) 1 = TCHBLK/CLK pins output TCHCLK (1-8) (transmit-channel block) Bit 2 / Receive-Frame/Multiframe Sync Select (RFMSS). This bit controls the function of all eight RF/RMSYNC pins. 0 = RF/RMSYNC pins output RFSYNC (1-8) (receive-frame sync) 1 = RF/RMSYNC pins output RMSYNC (1-8) (receive-multiframe sync) Bit 3 / Receive Loss-of-Signal/Signaling Freeze Select (RLOSSFS). This bit controls the function of all eight RLOS/RSIGF pins. 0 = RLOS/RSIGF pins output RLOS (1-8) (receive loss-of-signal) 1 = RLOS/RSIGF pins output RSIGF (1-8) (receive-signaling freeze) Bits 4, 5 / Backplane Clock Select 0-1 (BPCLK0/1). These bits determine the clock frequency output on the BPCLK pin. BPCLK1 0 0 1 1 BPCLK0 0 1 0 1 BPCLK Frequency (MHz) 2.048 4.096 8.192 16.384 Bits 6, 7 / Interleave Bus Operation Mode Select 0-1 (IBOMS0/1). These bits determine the configuration of the IBO (interleaved bus) multiplexer. These bits should be used with the Rx and Tx IBO control registers within each of the framer units. Additional information concerning the IBO mux is given in Section 7.3. IBOMS1 0 0 1 1 IBOMS0 0 1 0 1 IBO Mode IBO Mux Disabled 4.096MHz (2 per) 8.192MHz (4 per) 16.384MHz (8 per) 26 DS26401 Octal T1/E1/J1 Framer 7.3 IBO Multiplexer The IBO multiplexer is used with the IBO function located within each framer/formatter block (controlled by the RIBOC and TIBOC registers). When enabled, the IBO multiplexer simplifies user interface by connecting TDM bus signals internally. The IBO multiplexer eliminates the need for ganged external wiring and tri-state output drivers on the RSER and RSIG pins. The DS26401 also supports the traditional mode of IBO operation by allowing complete access to individual framers and tri-stating the RSER and RSIG pins at the appropriate times for external bus wiring. This operation mode is enabled per framer in the associated RIBOC and TIBOC registers, while leaving the IBO multiplexer disabled (IBOMS0 = 0 and IBOMS1 = 0). Figure 7-1, Figure 7-2, and Figure 7-3 show the equivalent internal circuit for each IBO mode. Table 7-1 describes the pin function changes for each mode of the IBO multiplexer. The transmit and receive IBO functions are described in Sections 8.21 (T1 XMIT), 9.20 (T1 REC), 10.17 (E1 XMIT), and 11.19 (E1 REC). 27 DS26401 Octal T1/E1/J1 Framer Figure 7-1. Internal IBO Multiplexer Equivalent Circuit--4.096MHz RSER1 RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSIG1 RSYNC1 RSYSCLK1 TSER1 TSIG1 TSSYNC1 TSYSCLK1 Port # 1 Backplane Interface Port # 2 Backplane Interface RSER3 RSIG3 RSYNC3 RSYSCLK3 TSER3 TSIG3 TSSYNC3 TSYSCLK3 Port # 3 Backplane Interface Port # 4 Backplane Interface RSER5 RSIG5 RSYNC5 RSYSCLK5 TSER5 TSIG5 TSSYNC5 TSYSCLK5 Port # 5 Backplane Interface Port # 6 Backplane Interface RSER7 RSIG7 RSYNC7 RSYSCLK7 TSER7 TSIG7 TSSYNC7 TSYSCLK7 Port # 7 Backplane Interface Port # 8 Backplane Interface 28 DS26401 Octal T1/E1/J1 Framer Figure 7-2. Internal IBO Multiplexer Equivalent Circuit--8.192MHz RSER1 RSIG1 RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSSYNC TSYSCLK TSER TSIG Port # 1 Backplane Interface RSYNC1 RSYSCLK1 TSER1 TSIG1 TSSYNC1 TSYSCLK1 Port # 2 Backplane Interface Port # 3 Backplane Interface Port # 4 Backplane Interface RSER5 RSIG5 RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK Port # 5 Backplane Interface RSYNC5 RSYSCLK5 TSER5 TSIG5 TSSYNC5 TSYSCLK5 Port # 6 Backplane Interface Port # 7 Backplane Interface Port # 8 Backplane Interface 29 DS26401 Octal T1/E1/J1 Framer Figure 7-3. Internal IBO Multiplexer Equivalent Circuit--16.394MHz RSER(1) RSER(2) RSER(3) RSER(4) RSER(5) RSER(6) RSER(7) RSER(8) RIBO_OEB(1-8) RSER1 RSIG(1) RSIG(2) RSIG(3) RSIG(4) RSIG(5) RSIG(6) RSIG(7) RSIG(8) RIBO_OEB(1-8) RSIG1 Port # 1 Backplane Interface RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK To Mux RSYNC1 RSYSCLK1 TSER1 TSIG1 TSSYNC1 TSYSCLK1 To Mux Port # 2 Backplane Interface To Mux Port # 3 Backplane Interface To Mux Port # 4 Backplane Interface To Mux Port # 5 Backplane Interface To Mux Port # 6 Backplane Interface To Mux Port # 7 Backplane Interface To Mux Port # 8 Backplane Interface 30 DS26401 Octal T1/E1/J1 Framer Table 7-1. Pin Functions with IBO Mux Enabled RSER Output Pin Definitions NAME RSER1 NORMAL USE Rx Serial Data for Port # 1 4.096MHz IBO Combined Rx Serial Data for Ports 1 & 2 Unused Combined Rx Serial Data for Ports 3 & 4 Unused Combined Rx Serial Data for Ports 5 & 6 Unused Combined Rx Serial Data for Ports 7 & 8 Unused 8.192MHz IBO Combined Rx Serial Data for Ports 1-4 Unused 16.384MHz IBO Rx Serial Data for Ports 1-8 Unused RSER2 Rx Serial Data for Port # 2 RSER3 Rx Serial Data for Port # 3 Unused Unused RSER4 Rx Serial Data for Port # 4 Unused Combined Rx Serial Data for Ports 5-8 Unused Unused RSER5 Rx Serial Data for Port # 5 Unused RSER6 Rx Serial Data for Port # 6 Unused RSER7 Rx Serial Data for Port # 7 Unused Unused RSER8 Rx Serial Data for Port # 8 Unused Unused RSIG Output Pin Definitions NAME NORMAL USE RSIG1 Rx Signaling Data for Port # 1 4.096MHz IBO Combined Rx Signaling Data for Ports 1 & 2 Unused Combined Rx Signaling Data for Ports 3 & 4 Unused Combined Rx Signaling Data for Ports 5 & 6 Unused Combined Rx Signaling Data for Ports 7 & 8 Unused 8.192MHz IBO Combined Rx Signaling Data for Ports 1-4 Unused 16.384MHz IBO Rx Signaling Data for Ports 1-8 Unused RSIG2 Rx Signaling Data for Port # 2 RSIG3 Rx Signaling Data for Port # 3 Unused Unused RSIG4 Rx Signaling Data for Port # 4 Unused Combined Rx Signaling Data for Ports 5-8 Unused Unused RSIG5 Rx Signaling Data for Port # 5 Unused RSIG6 Rx Signaling Data for Port # 6 Unused RSIG7 Rx Signaling Data for Port # 7 Unused Unused RSIG8 Rx Signaling Data for Port # 8 Unused Unused 31 DS26401 Octal T1/E1/J1 Framer Table 7-1. Pin Functions with IBO Mux Enabled (continued) TSER Input Pin Definitions NAME NORMAL USE TSER1 Tx Serial Data for Port # 1 4.096MHz IBO Combined Tx Serial Data for Ports 1 & 2 Unused Combined Tx Serial Data for Ports 3 & 4 Unused Combined Tx Serial Data for Ports 5 & 6 Unused Combined Tx Serial Data for Ports 7 & 8 Unused 8.192MHz IBO Combined Tx Serial Data for Ports 1-4 Unused 16.384MHz IBO Tx Serial Data for Ports 1-8 Unused TSER2 Tx Serial Data for Port # 2 TSER3 Tx Serial Data for Port # 3 Unused Unused TSER4 Tx Serial Data for Port # 4 Unused Combined Tx Serial Data for Ports 5-8 Unused Unused TSER5 Tx Serial Data for Port # 5 Unused TSER6 Tx Serial Data for Port # 6 Unused TSER7 Tx Serial Data for Port # 7 Unused Unused TSER8 Tx Serial Data for Port # 8 Unused Unused TSIG Input Pin Definitions NAME NORMAL USE TSIG1 Tx Signaling Data for Port # 1 4.096MHz IBO Combined Tx Signaling Data for Ports 1 & 2 Unused Combined Tx Signaling Data for Ports 3 & 4 Unused Combined Tx Signaling Data for Ports 5 & 6 Unused Combined Tx Signaling Data for Ports 7 & 8 Unused 8.192MHz IBO Combined Tx Signaling Data for Ports 1-4 Unused 16.384MHz IBO Tx Signaling Data for Ports 1-8 Unused TSIG2 Tx Signaling Data for Port # 2 TSIG3 Tx Signaling Data for Port # 3 Unused Unused TSIG4 Tx Signaling Data for Port # 4 Unused Combined Tx Signaling Data for Ports 5-8 Unused Unused TSIG5 Tx Signaling Data for Port # 5 Unused TSIG6 Tx Signaling Data for Port # 6 Unused TSIG7 Tx Signaling Data for Port # 7 Unused Unused TSIG8 Tx Signaling Data for Port # 8 Unused Unused 32 DS26401 Octal T1/E1/J1 Framer Table 7-1. Pin Functions with IBO Mux Enabled (continued) RSYNC Input Pin Definitions NAME NORMAL USE RSYNC1 Rx Frame Pulse for port # 1 4.096MHz IBO Rx Frame Pulse for Ports 1 & 2 Unused Rx Frame Pulse for Ports 3 & 4 Unused Rx Frame Pulse for Ports 5 & 6 Unused Rx Frame Pulse for Ports 7 & 8 Unused 8.192MHz IBO Rx Frame Pulse for Ports 1-4 Unused 16.384MHz IBO Rx Frame Pulse for Ports 1-8 Unused RSYNC2 Rx Frame Pulse for port # 2 RSYNC3 Rx Frame Pulse for port # 3 Unused Unused RSYNC4 Rx Frame Pulse for port # 4 Unused Rx Frame Pulse for Ports 5-8 Unused Unused RSYNC5 Rx Frame Pulse for port # 5 Unused RSYNC6 Rx Frame Pulse for port # 6 Unused RSYNC7 Rx Frame Pulse for port # 7 Unused Unused RSYNC8 Rx Frame Pulse for port # 8 Unused Unused TSSYNC Input Pin Definitions NAME TSSYNC1 NORMAL USE Tx Frame Pulse for Port # 1 4.096MHz IBO Tx Frame Pulse for Ports 1 & 2 Unused Tx Frame Pulse for Ports 3 & 4 Unused Tx Frame Pulse for Ports 5 & 6 Unused Tx Frame Pulse for Ports 7 & 8 Unused 8.192MHz IBO Tx Frame Pulse for Ports 1- 4 Unused 16.384MHz IBO Tx Frame Pulse for Ports 1-8 Unused TSSYNC2 Tx Frame Pulse for Port # 2 TSSYNC3 Tx Frame Pulse for Port # 3 Unused Unused TSSYNC4 Tx Frame Pulse for Port # 4 Unused Tx Frame Pulse for Ports 5-8 Unused Unused TSSYNC5 Tx Frame Pulse for Port # 5 Unused TSSYNC6 Tx Frame Pulse for Port # 6 Unused TSSYNC7 Tx Frame Pulse for Port # 7 Unused Unused TSSYNC8 Tx Frame Pulse for Port # 8 Unused Unused 33 DS26401 Octal T1/E1/J1 Framer Table 7-1. Pin Functions with IBO Mux Enabled (continued) RSYSCLK Input Pin Definitions NAME NORMAL USE RSYSCLK1 RSYSCLK2 Rx System Clock for port # 1 Rx System Clock for port # 2 4.096MHz IBO Rx System Clock for Ports 1 & 2 Unused Rx System Clock for Ports 3 & 4 Unused Rx System Clock for Ports 5 & 6 Unused Rx System Clock for Ports 7 & 8 Unused 8.192MHz IBO Rx System Clock for Ports 1- 4 Unused 16.384MHz IBO Rx System Clock for Ports 1- 8 Unused RSYSCLK3 Rx System Clock for port # 3 Unused Unused RSYSCLK4 Rx System Clock for port # 4 Unused Rx System Clock for Ports 5-8 Unused Unused RSYSCLK5 Rx System Clock for port # 5 Unused RSYSCLK6 Rx System Clock for port # 6 Unused RSYSCLK7 Rx System Clock for port # 7 Unused Unused RSYSCLK8 Rx System Clock for port # 8 Unused Unused TSYSCLK Input Pin Definitions NAME NORMAL USE TSYSCLK1 Tx System Clock for Port # 1 4.096MHz IBO Tx System Clock for Ports 1 & 2 Unused Tx System Clock for Ports 3 & 4 Unused Tx System Clock for Ports 5 & 6 Unused Tx System Clock for Ports 7 & 8 Unused 8.192MHz IBO Tx System Clock for Ports 1-4 Unused 16.384MHz IBO Tx System Clock for Ports 1- 8 Unused TSYSCLK2 Tx System Clock for Port # 2 TSYSCLK3 Tx System Clock for Port # 3 Unused Unused TSYSCLK4 Tx System Clock for Port # 4 Unused Tx System Clock for Ports 5-8 Unused Unused TSYSCLK5 Tx System Clock for Port # 5 Unused TSYSCLK6 Tx System Clock for Port # 6 Unused TSYSCLK7 Tx System Clock for Port # 7 Unused Unused TSYSCLK8 Tx System Clock for Port # 8 Unused Unused 34 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 ID7 0 IDR Device Identification Register 0F8h 6 ID6 0 5 ID5 0 4 ID4 0 3 ID3 0 2 ID2 0 1 ID1 0 0 ID0 0 Bits 0 to 3/Chip Revision Bits (ID0 to ID3). The lower four bits of the IDR are used to display the die revision of the chip. IDO is the LSB of a decimal code that represents the chip revision. Bits 4 to 7/Device ID (ID4 to ID7). The upper four bits of the IDR are used to display the DS26401 ID. DEVICE DS26401 ID (ID4 to ID7) 8h 35 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 FIS8 0 GSR1 Global Status Register 1 0F9h 6 FIS7 0 5 FIS6 0 4 FIS5 0 3 FIS4 0 2 FIS3 0 1 FIS2 0 0 FIS1 0 Note: The GSR1 register reports the framer interrupt status for each of the 8 T1/E1 framers. A logic 1 in the associated bit location indicates a framer has set (active low) its interrupt signal. Bit 0 / Framer Interrupt Status 1 (FIS1) 0 = Framer 1 has not issued an interrupt 1 = Framer 1 has issued an interrupt Bit 1 / Framer Interrupt Status 2 (FIS2) 0 = Framer 2 has not issued an interrupt 1 = Framer 2 has issued an interrupt Bit 2 / Framer Interrupt Status 3 (FIS3) 0 = Framer 3 has not issued an interrupt 1 = Framer 3 has issued an interrupt Bit 3 / Framer Interrupt Status 4 (FIS4) 0 = Framer 4 has not issued an interrupt 1 = Framer 4 has issued an interrupt Bit 4 / Framer Interrupt Status 5 (FIS5) 0 = Framer 5 has not issued an interrupt 1 = Framer 5 has issued an interrupt Bit 5 / Framer Interrupt Status 6 (FIS6) 0 = Framer 6 has not issued an interrupt 1 = Framer 6 has issued an interrupt Bit 6 / Framer Interrupt Status 7 (FIS7) 0 = Framer 7 has not issued an interrupt 1 = Framer 7 has issued an interrupt Bit 7 / Framer Interrupt Status 8 (FIS8) 0 = Framer 8 has not issued an interrupt 1 = Framer 8 has issued an interrupt 36 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: GSR2 Global Status Register 2 0FAh Bit # Name Default 7 -- 0 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 -- 0 1 BBED 0 0 BLOS 0 Bit 0 / BERT Loss-of-Sync Interrupt Status (BLOS) 0 = The BERT has not issued an interrupt for LOS 1 = The BERT has issued an interrupt for LOS (only possible when BLOSIM in GCR1 is set) Bit 1 / BERT Bit-Error-Detect Interrupt Status (BBED) 0 = The BERT has not issued an interrupt for BED 1 = The BERT has issued an interrupt for BED (only possible when BBEDIM in GCR1 is set) Bits 2-7 / Unused 7.4 Interrupt Tree When the host processor detects an interrupt, the user can first read the GSR1 and GSR2 registers to narrow down the potential source of the interrupt event. Bit locations set in the GSR1 register direct the user to one or more framers, from where the appropriate status register(s) can be discerned with RIIR and TIIR. INTERRUPT GSR1 (0F9h) FIS8 FIS7 FIS6 FIS5 FIS4 FIS3 FIS2 FIS1 E9Fh C9Fh A9Fh 89Fh 69Fh 49Fh 29Fh F9Fh D9Fh B9Fh 99Fh 79Fh 59Fh 39Fh To Framer(n) Latched Status Registers GSR2 (0FAh) BBED BLOS BSR (2F4h) TIIR (19Fh) TLS2 TLS1 RIIR (09Fh) -- RLS7 RLS6 RLS5 RLS4 RLS3 RLS2 RLS1 Framer for Port #1 (A11:A9 = 000b) NOTE: RLS2 IS NOT USED IN T1 MODE; RLS7 IS NOT USED IN E1 MODE. 37 DS26401 Octal T1/E1/J1 Framer 8. T1 RECEIVER 8.1 T1 Receiver Register Map ADDRESS 000 001 002 003 004 005 006 007 008 009 00A 00B 00C 00D 00E 00F 010 011 012 013 014 015 016 017 018 019 01A 01B 01C 01D 01E 01F 020 021 022 023 024 025 026 027 028 029 02A 02B 02C 02D 02E 02F 030 031 032 033 034 035 036 R/W -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- R/W R/W R/W R/W R/W R/W -- -- -- -- -- -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W FUNCTION Unused (See note) Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Rx HDLC Control Rx HDLC Bit Suppress Rx DS0 Monitor Select Rx Signaling Control Rx Control 2 Rx BOC Control Unused Unused Unused Unused Unused Unused Rx Test Register 1 Rx Test Register 2 Rx Test Register 3 Rx Test Register 4 Rx Idle Definition 1 Rx Idle Definition 2 Rx Idle Definition 3 Rx Idle Definition 4 Rx Idle Definition 5 Rx Idle Definition 6 Rx Idle Definition 7 Rx Idle Definition 8 Rx Idle Definition 9 Rx Idle Definition 10 Rx Idle Definition 11 Rx Idle Definition 12 Rx Idle Definition 13 Rx Idle Definition 14 Rx Idle Definition 15 Rx Idle Definition 16 Rx Idle Definition 17 Rx Idle Definition 18 Rx Idle Definition 19 Rx Idle Definition 20 Rx Idle Definition 21 Rx Idle Definition 22 Rx Idle Definition 23 NAME -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- RHC RHBSE RDS0SEL RSIGC RCR2 RBOCC -- -- -- -- -- -- RTEST1 RTEST2 RTEST3 RTEST4 RIDR1 RIDR2 RIDR3 RIDR4 RIDR5 RIDR6 RIDR7 RIDR8 RIDR9 RIDR10 RIDR11 RIDR12 RIDR13 RIDR14 RIDR15 RIDR16 RIDR17 RIDR18 RIDR19 RIDR20 RIDR21 RIDR22 RIDR23 PAGE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 200 200 181 184 159 83 -- -- -- -- -- -- -- -- -- -- 187 187 187 187 187 187 187 187 187 187 187 187 187 187 187 187 187 187 187 187 187 187 187 38 DS26401 Octal T1/E1/J1 Framer ADDRESS 037 038 039 03A 03B 03C 03D 03E 03F 040 041 042 043 044 045 046 047 048 049 04A 04B 04C 04D 04E 04F 050 051 052 053 054 055 056 057 058 059 05A 05B 05C 05D 05E 05F 060 061 062 063 064 065 066 067 068 069 06A 06B 06C 06D 06E 06F 070 071 072 073 R/W R/W R/W R/W R/W -- R/W R/W R/W -- R R R R R R R R R R R R -- -- -- -- R R R R R R -- -- -- -- -- -- -- -- -- -- R -- R R R R R -- -- -- -- -- -- -- -- -- -- -- -- -- FUNCTION Rx Idle Definition 24 Rx Sig All Ones Insertion 1 Rx Sig All Ones Insertion 2 Rx Sig All Ones Insertion 3 Unused Rx Digital Milliwatt Enable 1 Rx Digital Milliwatt Enable 2 Rx Digital Milliwatt Enable 3 Unused Rx Signaling 1 Rx Signaling 2 Rx Signaling 3 Rx Signaling 4 Rx Signaling 5 Rx Signaling 6 Rx Signaling 7 Rx Signaling 8 Rx Signaling 9 Rx Signaling 10 Rx Signaling 11 Rx Signaling 12 Unused Unused Unused Unused Rx Line-Code Violation Counter 1 Rx Line-Code Violation Counter 2 Rx Path-Code Violation Count 1 Rx Path-Code Violation Count 2 Rx Frames Out-of-Sync Counter 1 Rx Frames Out-of-Sync Counter 2 Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Rx DS0 Monitor Unused Rx FDL Rx BOC Rx SLC96 Data Link 1 Rx SLC96 Data Link 2 Rx SLC96 Data Link 3 Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused NAME RIDR24 RSAOI1 RSAOI2 RSAOI3 -- RDMWE1 RDMWE2 RDMWE3 -- RS1 RS2 RS3 RS4 RS5 RS6 RS7 RS8 RS9 RS10 RS11 RS12 -- -- -- -- LCVCR1 LCVCR2 PCVCR1 PCVCR2 FOSCR1 FOSCR2 -- -- -- -- -- -- -- -- -- -- RDS0M -- RFDL RBOC RSLC1 RSLC2 RSLC3 -- -- -- -- -- -- -- -- -- -- -- -- -- PAGE 187 75 75 75 -- 63 63 63 -- 185 185 185 185 185 185 185 185 185 185 185 185 -- -- -- -- 66 66 67 67 68 68 -- -- -- -- -- -- -- -- -- -- 181 -- 86 84 85 85 85 -- -- -- -- -- -- -- -- -- -- -- -- -- 39 DS26401 Octal T1/E1/J1 Framer ADDRESS 074 075 076 077 078 079 07A 07B 07C 07D 07E 07F 080 081 082 083 084 085 086 087 088 089 08A 08B 08C 08D 08E 08F 090 091 092 093 094 095 096 097 098 099 09A 09B 09C 09D 09E 09F 0A0 0A1 0A2 0A3 0A4 0A5 0A6 0A7 0A8 0A9 0AA 0AB 0AC 0AD 0AE 0AF 0B0 R/W -- -- -- -- -- -- -- -- -- -- -- -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W -- -- R/W R/W R/W R/W R/W R/W R/W -- R/W -- R/W R/W R/W -- R/W R/W -- R/W R/W -- R/W R/W R/W -- R/W -- R/W R/W R/W -- R/W R/W R/W R/W R FUNCTION Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Rx Master Mode Rx Control 1 Rx In-Band Code Control Rx Control 3 Rx I/O Configuration Rx Elastic Store Control Rx Error Count Configuration Rx HDLC FIFO Control Rx Interleave Bus Op Control Rx Spare Code Control Rx BERT Interface Control Rx BERT Bit Suppress En Unused Unused Rx Test Register 5 Rx Test Register 6 Rx Latched Status 1 Rx Latched Status 2 Rx Latched Status 3 Rx Latched Status 4 Rx Latched Status 5 Unused Rx Latched Status 7 Unused Rx Signaling CoS Status 1 Rx Signaling CoS Status 2 Rx Signaling CoS Status 3 Unused Rx Spare Code Definition 1 Rx Spare Code Definition 2 Unused Rx Interrupt Information Reg Rx Interrupt Mask Reg 1 Unused Rx Interrupt Mask Reg 3 Rx Interrupt Mask Reg 4 Rx Interrupt Mask Reg 5 Unused Rx Interrupt Mask Reg 7 Unused Rx Sig CoS Interrupt Enable 1 Rx Sig CoS Interrupt Enable 2 Rx Sig CoS Interrupt Enable 3 Unused Rx Up-Code Definition 1 Rx Up-Code Definition 2 Rx Down-Code Definition 1 Rx Down-Code Definition 2 Rx Real-Time Status 1 NAME -- -- -- -- -- -- -- -- -- -- -- -- RMMR RCR1 RIBCC RCR3 RIOCR RESCR ERCNT RHFC RIBOC RSCC RBICR RBBS -- -- RTEST5 RTEST6 RLS1 RLS2 RLS3 RLS4 RLS5 -- RLS7 -- RSS1 RSS2 RSS3 -- RSPCD1 RSPCD2 -- RIIR RIM1 -- RIM3 RIM4 RIM5 -- RIM7 -- RSCSE1 RSCSE2 RSCSE3 -- RUPCD1 RUPCD2 RDNCD1 RDNCD2 RRTS1 PAGE -- -- -- -- -- -- -- -- -- -- -- -- 156 158 87 160 161 190 65 201 209 90 210 211 -- -- -- -- 166 168 170 173 205 -- -- 74 74 74 -- 87 87 -- 157 167 -- 171 174 206 -- -- 186 186 186 -- 88 88 89 89 165 40 DS26401 Octal T1/E1/J1 Framer ADDRESS 0B1 0B2 0B3 0B4 0B5 0B6 0B7 0B8 0B9 0BA 0BB 0BC 0BD 0BE 0BF 0C0 0C1 0C2 0C3 0C4 0C5 0C6 0C7 0C8 0C9 0CA 0CB 0CC 0CD 0CE 0CF 0D0 0D1 0D2 0D3 0D4 0D5 0D6 0D7 0D8 0D9 0DA 0DB 0DC 0DD 0DE 0DF 0E0 0E1 0E2 0E3 0E4 0E5 0E6 0E7 0E8 0E9 0EA 0EB 0EC 0ED R/W -- R -- R R R -- -- -- -- -- -- -- -- -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W -- R/W R/W R/W -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- FUNCTION Unused Rx Real-Time Status 3 Unused Rx Real-Time Status 5 (HDLC) Rx HDLC Packet Bytes Available Rx HDLC FIFO Unused Unused Unused Unused Unused Unused Unused Unused Unused Rx Blank Channel Select 1 Rx Blank Channel Select 2 Rx Blank Channel Select 3 Rx Blank Channel Select 4 Rx Channel Blocking 1 Rx Channel Blocking 2 Rx Channel Blocking 3 Rx Channel Blocking 4 Rx Signaling Insertion 1 Rx Signaling Insertion 2 Rx Signaling Insertion 3 Rx Signaling Insertion 4 Rx Gapped Clock Channel Select 1 Rx Gapped Clock Channel Select 2 Rx Gapped Clock Channel Select 3 Rx Gapped Clock Channel Select 4 Rx Channel Idle Code Enable 1 Rx Channel Idle Code Enable 2 Rx Channel Idle Code Enable 3 Unused Rx BERT Channel Select 1 Rx BERT Channel Select 2 Rx BERT Channel Select 3 Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused NAME -- RRTS3 -- RRTS5 RHPBA RHF -- -- -- -- -- -- -- -- -- RBCS1 RBCS2 RBCS3 RBCS4 RCBR1 RCBR2 RCBR3 RCBR4 RSI1 RSI2 RSI3 RSI4 RGCCS1 RGCCS2 RGCCS3 RGCCS4 RCICE1 RCICE2 RCICE3 -- RBCS1 RBCS2 RBCS3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PAGE -- 169 -- 204 202 203 -- -- -- -- -- -- -- -- -- 191 191 191 191 188 188 188 188 186 186 186 186 193 193 193 193 187 187 187 -- 191 191 191 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 41 DS26401 Octal T1/E1/J1 Framer ADDRESS 0EE 0EF 0F0 0F1 0F2 0F3 0F4 0F5 0F6 0F7 0F8 0F9 0FA 0FB 0FC 0FD 0FE 0FF R/W -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- FUNCTION Unused Unused Used by Global Functions Used by Global Functions Unused Unused Unused Unused Unused Unused Used by Global Functions Used by Global Functions Used by Global Functions Unused Unused Unused Unused Unused NAME -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PAGE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Note: All unused addresses should be set to 0. 42 DS26401 Octal T1/E1/J1 Framer 8.2 T1 Receive Framer Description and Operation The DS26401 includes eight fully independent DS1/E1 framers. The framers are designed to interface seamlessly to the line side through an external LIU. Each framer can be individually programmed to accept AMI, B8ZS, HDB3, or NRZ data. In T1 mode, each framer supports D4 (SF), ESF, and SLC-96 frame formats, and detects/reports common alarms such as AIS, RAI, LOS, and OOF, as well as AIS-CI and RAI-CI. Performance monitor counters are maintained for each port, which report bipolar/line-code violations, F-bit/CRC errors, and number of out-of-sync multiframes. Each framer has an HDLC controller that can be mapped into a single time slot, or Sa4 to Sa8 bits (E1 mode), or the FDL (T1 mode), and has 64-byte FIFO buffers in both the transmit and receive paths. The HDLC controllers perform the necessary overhead for generating and receiving performance report messages (PRM) as described in ANSI T1.403 and the messages as described in AT&T TR54016. The HDLC controllers automatically generate and detect flags; generate and check the CRC checksum; generate and detect abort sequences and stuff and destuff zeros; and byte align to the data stream. The FIFO buffers are large enough to allow a full PRM to be received or transmitted without host intervention. Other features contained within each framer include a BOC detector with programmable code integration and three independent 16-bit loop-code detectors. Host interface is simplified with status registers optimized for either interrupt driven or polled environments. In many cases, status bits are reported in both real-time and latched on change-of-state with separate bits for each state change. Most latched bits can be mapped to generate an external interrupt on the INT pin. Backplane interface is simplified with the inclusion of two-frame elastic-store memories in each of the receive and transmit paths. These buffers can be used to control slips in asynchronous environments, or rate-adapt from 1.544MHz to 2.048MHz. The DS26401 also supports an interleaved backplane operating at 4.096MHz, 8.192MHz, or 16.384MHz. Additional details about the operation of the DS1 framer are included in the register descriptions in this section. 43 DS26401 Octal T1/E1/J1 Framer 8.3 Receive Master-Mode Register The receive master-mode register (RMMR) controls the initialization of the receive-side framer. The FRM_EN bit can be left low if the framer for that particular port is not going to be used, putting the circuit in a low-power (sleep) state. Register Name: Register Description: Register Address: Bit # Name Default 7 FRM_EN 0 RMMR Receive Master Mode Register 080h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 INIT_DONE 0 5 -- 0 4 -- 0 3 -- 0 2 -- 0 1 SFTRST 0 0 T1/E1 0 Bit 0 / Receiver T1/E1 Mode Select (T1/E1). This bit sets the operating mode for receiver only! This bit must be set to the desired state before writing INIT_DONE. 0 = T1 operation 1 = E1 operation Bit 1 / Soft Reset (SFTRST). Level-sensitive processor reset. Should be taken high, then low to reset and initialize the internal processor. 0 = Normal operation 1 = Hold the internal RISC in reset. This bit only affects the receive-side processor. Bits 2-5 / Unused. Must be set = 0 for proper operation. Bit 6 / Initialization Done (INIT_DONE). The host (user) must set this bit once the configuration registers have been written. The host is required to write or clear all RAM based registers (addresses 00H to 7FH) prior to setting this bit. Once INIT_DONE is set, the internal processor will check the FRM_EN bit. If enabled, the internal processor continues executing based on the initial configuration. Bit 7 / Framer Enable (FRM_EN). This bit must be written with the desired value prior to setting INIT_DONE. 0 = Framer disabled (held in low-power state) 1 = Framer enabled (all features active) 8.4 Interrupt Information Register The interrupt information registers provide an indication of which DS26401 status registers are generating an interrupt. When an interrupt occurs, the host can read RIIR to quickly identify which of the seven T1 receive status registers is causing the interrupt(s). The interrupt information register bits clear once the appropriate interrupt has been serviced and cleared, as long as no other interrupt condition is present in the associated status register. Status bits that have been masked through the receive-interrupt mask (RIMx) registers are also masked from the RIIR register. Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 RIIR Receive Interrupt Information Register 9Fh + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 RLS7 0 5 RLS6 0 4 RLS5 0 3 RLS4 0 2 RLS3 0 1 RLS2* 0 0 RLS1 0 *RLS2 does not create an interrupt, therefore this bit is not used in T1 mode. 44 DS26401 Octal T1/E1/J1 Framer 8.5 T1 Receive Control Registers These registers provide the primary setup and control of the receive framers. Register Name: Register Description: Register Address: Bit # Name Default 7 SYNCT 0 RCR1 Receive Control Register 1 081h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 RB8ZS 0 5 RFM 0 4 ARC 0 3 SYNCC 0 2 RJC 0 1 SYNCE 0 0 RESYNC 0 Bit 0 / Resynchronize (RESYNC). When toggled from low to high, a resynchronization of the receive-side framer is initiated. Must be cleared and set again for a subsequent resync. Bit 1 / Sync Enable (SYNCE) 0 = auto resync enabled 1 = auto resync disabled Bit 2 / Receive Japanese CRC6 Enable (RJC) 0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation) 1 = use Japanese standard JT-G704 CRC6 calculation Bit 3 / Sync Criteria (SYNCC) In D4 Framing Mode: 0 = search for Ft pattern, then search for Fs pattern 1 = cross couple Ft and Fs pattern In ESF Framing Mode: 0 = search for FPS pattern only 1 = search for FPS and verify with CRC6 Bit 4 / Auto Resync Criteria (ARC) 0 = Resync on OOF or LOS event 1 = Resync on OOF only Bit 5 / Receive Frame Mode Select (RFM) 0 = ESF framing mode 1 = D4 framing mode Bit 6 / Receive B8ZS Enable (RB8ZS) 0 = B8ZS disabled 1 = B8ZS enabled Bit 7 / Sync Time (SYNCT) 0 = qualify 10 bits 1 = qualify 24 bits 45 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 RCR2 Receive Control Register 2 014h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 -- 0 4 RSLC96 0 3 OOF2 0 2 OOF1 0 1 RAIIE 0 0 RD4RM 0 Bit 0 / Receive-Side D4 Remote Alarm Select (RD4RM) 0 = zeros in bit 2 of all channels 1 = a one in the S-bit position of frame 12 (J1 Yellow Alarm Mode) Bit 1 / Receive RAI Integration Enable (RAIIE). The ESF RAI indication can be interrupted for a period not to exceed 100ms per interruption (T1.403). In ESF mode, setting RAIIE causes the RAI status from the DS26401 to be integrated for 200ms. 0 = RAI detects when 16 consecutive patterns of 00FF appear in the FDL. RAI clears when 14 or less patterns of 00FF hex out of 16 possible appear in the FDL. 1 = RAI detects when the condition has been present for greater than 200ms. RAI clears when the condition has been absent for greater than 200ms. Bits 2, 3 / Out-of-Frame Select Bits (OOF2, OOF1) OOF2 0 0 1 1 OOF1 0 1 0 1 OUT OF FRAME CRITERIA 2/4 frame bits in error 2/5 frame bits in error 2/6 frame bits in error 2/6 frame bits in error Bit 4 / Receive SLC-96 Synchronizer Enable (RSLC96). See Section 8.17. 0 = the SLC-96 synchronizer is disabled 1 = the SLC-96 synchronizer is enable Bits 5-7 / Unused. Must be set = 0 for proper operation. 46 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 IDF 0 RCR3 Receive Control Register 3 083h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 RSERC 0 4 -- 0 3 -- 0 2 RLB 0 1 PLB 0 0 FLB 0 Bit 0 / Framer Loopback (FLB) 0 = loopback disabled 1 = loopback enabled RPOS RNEG RECEIVE FRAMER BACKPLANE I/F RSER TPOS TNEG TRANSMIT FRAMER BACKPLANE I/F TSER FRAMER LOOPBACK This loopback is useful in testing and debugging applications. In FLB, the DS26401 loops data from the transmit side back to the receive side. When FLB is enabled, the following occurs: 1) (T1 mode) An unframed all-ones code is transmitted at TPOS and TNEG. (E1 mode) Normal data is transmitted at TPOS and TNEG. 2) Data at RPOS and RNEG is ignored. 3) All receive-side signals take on timing synchronous with TCLK instead of RCLK. Bit 1 / Payload Loopback (PLB) 0 = loopback disabled 1 = loopback enabled RPOS RNEG RECEIVE FRAMER BACKPLANE I/F RSER TPOS TNEG TRANSMIT FRAMER BACKPLANE I/F TSER PAYLOAD LOOPBACK (CAN BE DONE ON A PER-CHANNEL BASIS) When PLB is enabled, the following occurs: 1) Data is transmitted from the TPOS and TNEG pins synchronous with RCLK instead of TCLK. 2) All the receive-side signals continue to operate normally. 3) The TCHCLK and TCHBLK signals are forced low. 4) Data at the TSER, TDATA, and TSIG pins is ignored. 5) The TLCLK signal becomes synchronous with RCLK instead of TCLK. 47 DS26401 Octal T1/E1/J1 Framer Normally, this loopback is only enabled when ESF framing is being performed, but it can also be enabled in D4 framing applications. In a PLB situation, the DS26401 loops the 192 bits of payload data (with BPVs corrected) from the receive section back to the transmit section. The FPS framing pattern, CRC6 calculation, and the FDL bits are not looped back, they are reinserted by the DS26401. Bit 2 / Remote Loopback (RLB) 0 = loopback disabled 1 = loopback enabled RPOS RNEG RECEIVE FRAMER BACKPLANE I/F RSER TPOS TNEG TRANSMIT FRAMER BACKPLANE I/F TSER REMOTE LOOPBACK In this loopback, data input through the RPOS and RNEG pins is transmitted back to the TPOS and TNEG pins. Data continues to pass through the DS26401's receive-side framer as it would normally, and the data from the transmit-side formatter is ignored. Bits 3, 4, 6 / Unused. Must be set = 0 for proper operation. Bit 5 / RSER Control (RSERC) 0 = Allow RSER to output data as received under all conditions (normal operation) 1 = Force RSER to one under loss-of-frame alignment conditions Bit 7 / Input Data Format (IDF) 0 = Bipolar data is expected at RPOS and RNEG (either AMI or B8ZS). 1 = NRZ data is expected at RPOS. The BPV counter is disabled and RNEG is ignored by the DS26401. 48 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 RCLKINV RIOCR Receive I/O Configuration Register 084h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 RSYNCINV 5 H100EN 4 RSCLKM 0 0 0 0 3 RSMS 0 2 RSIO 0 1 RSMS2 0 0 RSMS1 0 Bit 0 / RSYNC Mode Select 1 (RSMS1). Selects frame or multiframe pulse when RSYNC pin is in output mode. In input mode (elastic store must be enabled) multiframe mode is only useful when receive signaling reinsertion is enabled. 0 = frame mode 1 = multiframe mode Bit 1 / RSYNC Mode Select 2 (RSMS2) T1: RSYNC pin must be programmed in the output frame mode 0 = do not pulse double wide in signaling frames 1 = do pulse double wide in signaling frames E1: RSYNC pin must be programmed in the output multiframe mode 0 = RSYNC outputs CAS multiframe boundaries 1 = RSYNC outputs CRC4 multiframe boundaries Bit 2 / RSYNC I/O Select (RSIO). (Note: This bit must be set to zero when elastic store is disabled) 0 = RSYNC is an output 1 = RSYNC is an input (only valid if elastic store enabled) Bit 3 / RSYNC Multiframe Skip Control (RSMS). This bit is useful in framing format conversions from D4 to ESF. This function is not available when the receive-side elastic store is enabled. RSYNC must be set to output multiframe pulses. 0 = RSYNC outputs a pulse at every multiframe. 1 = RSYNC outputs a pulse at every other multiframe. Bit 4 / RSYSCLK Mode Select (RSCLKM) 0 = if RSYSCLK is 1.544MHz 1 = if RSYSCLK is 2.048MHz or IBO enabled Bit 5 / H.100 SYNC Mode (H100EN). See additional details in Section 8.6. 0 = Normal operation 1 = RSYNC and TSSYNC signals are shifted. Bit 6 / RSYNC Invert (RSYNCINV) 0 = No inversion 1 = Invert RSYNC output Bit 7 / RCLK Invert (RCLKINV) 0 = No inversion 1 = Invert RCLK as input 49 DS26401 Octal T1/E1/J1 Framer 8.6 H.100 (CT Bus) Compatibility The H.100 (or CT Bus) is a synchronous, bit-serial, TDM transport bus operating at 8.192MHz. The H.100 standard also allows compatibility modes to operate at 2.048MHz, 4.096MHz, or 8.192MHz. The control bit H100EN (RIOCR.5), when combined with RSYNCINV and TSSYNCINV, allows the DS26401 to accept a CT-Bus-compatible frame-sync signal (CT_FRAME) at the RSYNC and TSSYNC inputs. The following rules apply to the H100EN control bit: 1) The H100EN bit controls the sampling point for the RSYNC (input mode) and TSSYNC only. (The RSYNC output and other sync signals are not affected.) 2) The H100EN bit is always used with the receive and transmit elastic store buffers. 3) The H100EN bit is typically used with 8.192MHz IBO mode (Section 8.21), but can also be used with 4.096MHz IBO mode or 2.048MHz backplane operation. 4) The H100EN bit in RIOCR controls both RSYNC and TSSYNC (i.e., there is no separate control bit for the TSSYNC). 5) The H100EN bit does not invert the expected signal; RSYNCINV (RIOCR) and TSSYNCINV (TIOCR) must be set high to invert the inbound sync signals. Figure 8-1. RSYNC Input in H.100 (CT Bus) Mode RSYNC1 RSYNC2 RSYSCLK RSER Bit 8 Bit 1 Bit 2 tbc3 NOTE 1: RSYNC INPUT MODE, IN NORMAL OPERATION NOTE 2: RSYNC INPUT MODE, H100EN = 1 AND RSYNCINV = 1. NOTE 3: tbc (BIT CELL TIME) = 122ns (typ). tbc = 244ns OR 488ns ALSO ACCEPTABLE. 50 DS26401 Octal T1/E1/J1 Framer Figure 8-2. TSSYNC Input in H.100 (CT Bus) Mode TSSYNC1 TSSYNC2 TSYSCLK TSER Bit 8 Bit 1 Bit 2 tbc3 NOTE 1: TSSYNC IN NORMAL OPERATION. NOTE 2. TSSYNC WITH H100EN = 1 AND TSSYNCINV = 1. NOTE 3: tbc (BIT CELL TIME) = 122ns (typ). tbc = 244ns OR 488ns ALSO ACCEPTABLE. 51 DS26401 Octal T1/E1/J1 Framer 8.7 T1 Receive Status and Information When a particular event has occurred (or is occurring), the appropriate bit in one of these registers is set to 1. Status bits can operate in either a latched or real-time fashion. Some latched bits can be enabled to generate a hardware interrupt through the INT signal. Real-Time Bits Some status bits operate in a real-time fashion. These bits are read-only and indicate the present state of an alarm or a condition. Real-time bits remain stable and valid during the host read operation. The current value of the internal status signals can be read at any time from the real-time status registers without changing any of the latched status register bits. Latched Bits When an event or an alarm occurs and a latched bit is set to 1, it remains set until the user clears it. These bits typically respond on a change-of-state for an alarm, condition, or event, and operate in a read-then-write fashion. The user should read the value of the desired status bit and then write a 1 to that particular bit location to clear the latched value (write a zero to locations not to be cleared). Once the bit is cleared, it is not set again until the event has occurred again. Mask Bits Some of the alarms and events can be either masked or unmasked from the interrupt pin through the interrupt mask registers (RIMx). When unmasked, the INT signal is forced low when the enabled event or condition occurs. The INT pin is allowed to return high (if no other unmasked interrupts are present) when the user reads, then clears (with a write) the alarm bit that caused the interrupt to occur. Note that the latched status bit and the INT pin clear even if the alarm is still present. Note that some conditions can have multiple status indications. For example, receive loss-of-frame (RLOF) provides the following indications: Real-time indication that the receiver is not synchronized with incoming data stream. Read-only bit that remains high as long as the condition is present. Latched indication that the receiver has lost synchronization since the bit was last cleared. Bit will clear when written by the user, even if the condition is still present (rising edge detect of RRTS1.0). Latched indication that the receiver has reacquired synchronization since the bit was last cleared. Bit will clear when written by the user, even if the condition is still present (falling edge detect of RRTS1.0). RRTS1.0 (RLOF) RLS1.0 (RLOFD) RLS1.4 (RLOFC) 52 DS26401 Octal T1/E1/J1 Framer Table 8-1. T1 Alarm Criteria ALARM AIS (Blue Alarm) (Note 1) RAI (Yellow Alarm) 1) D4 Bit 2 Mode (RCR2.0 = 0) SET CRITERIA CLEAR CRITERIA When over a 3ms window, 5 or fewer zeros are received When bit 2 of 256 consecutive channels is set to zero for at least 254 occurrences When the 12th framing bit is set to one for two consecutive occurrences When over a 3ms window, 6 or more zeros are received When bit 2 of 256 consecutive channels is set to zero for less than 254 occurrences When the 12th framing bit is set to zero for two consecutive occurrences 2) D4 12th F-Bit Mode (RCR2.0 = 1; also referred to as the Japanese Yellow Alarm) 3) ESF Mode When 16 consecutive patterns of 00FF appear in the FDL When 192 consecutive zeros are received When 14 or less patterns of 00FF hex out of 16 possible appear in the FDL When 14 or more ones out of 112 possible bit positions are received starting with the first one received LOS (also referred to as Receive Carrier Loss (RCL)) Note 1: The definition of the Alarm Indication Signal (Blue Alarm) is an unframed all-ones signal. AIS detectors should be able to operate properly in the presence of a 10E-3 error rate, and they should not falsely trigger on a framed all-ones signal. The AIS alarm criteria in the DS26401 has been set to achieve this performance. It is recommended that the RAIS bit be qualified with the RLOF bit. Note 2: The following terms are equivalent: RAIS = Blue Alarm RLOS = RCL RLOF = Loss of Frame RRAI = Yellow Alarm Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 RRTS1 Receive Real-Time Status Register 1 0B0h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 -- 0 4 -- 0 3 RRAI 0 2 RAIS 0 1 RLOS 0 0 RLOF 0 All bits in this register are real-time (not latched). Bit 0 / Receive Loss-of-Frame Condition (RLOF). Set when the DS26401 is not synchronized to the received data stream. Bit 1 / Receive Loss-of-Signal Condition (RLOS). Set when 192 consecutive zeros have been detected at RPOS and RNEG. Bit 2 / Receive Alarm Indication Signal Condition (RAIS). Set when an unframed all-ones code is received at RPOS and RNEG. Bit 3 / Receive Remote Alarm Indication Condition (RRAI). Set when a remote alarm is received at RPOS and RNEG. Bits 4 to 7 / Unused 53 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 RRAIC 0 RLS1 Receive Latched Status Register 1 090h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 RAISC 0 5 RLOSC 0 4 RLOFC 0 3 RRAID 0 2 RAISD 0 1 FLOSD 0 0 RLOFD 0 All bits in this register are latched and can create interrupts. Bit 0 / Receive Loss-of-Frame Condition Detect (RLOFD). Rising edge detect of RLOF. Set when the DS26401 has lost synchronized to the received data stream. Bit 1 / Receive Loss-of-Signal Condition Detect (RLOSD). Rising edge detect of RLOS. Set when 192 consecutive zeros have been detected at RPOS and RNEG. Bit 2 / Receive Alarm Indication Signal Condition Detect (RAISD). Rising edge detect of RAIS. Set when an unframed all-ones code is received at RPOS and RNEG. Bit 3 / Receive Remote Alarm Indication Condition Detect (RRAID). Rising edge detect of RRAI. Set when a remote alarm is received at RPOS and RNEG. Bit 4 / Receive Loss-of-Frame Condition Clear (RLOFC). Falling edge detect of RLOF. Set when an RLOF condition has cleared. Bit 5 / Receive Loss-of-Signal Condition Clear (RLOSC). Falling edge detect of RLOS. Set when an RLOS condition has cleared. Bit 6 / Receive Alarm Indication Signal Condition Clear (RAISC). Falling edge detect of RAIS. Set when a RAIS condition has cleared. Bit 7 / Receive Remote Alarm Indication Condition Clear (RRAIC). Falling edge detect of RRAI. Set when a RRAI condition has cleared. 54 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 RRAIC 0 RIM1 Receive Interrupt Mask Register 1 0A0h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 RAISC 0 5 RLOSC 0 4 RLOFC 0 3 RRAID 0 2 RAISD 0 1 RLOSD 0 0 RLOFD 0 Bit 0 / Receive Loss-of-Frame Condition Detect (RLOFD) 0 = interrupt masked 1 = interrupt enabled Bit 1 / Receive Loss-of-Signal Condition Detect (RLOSD) 0 = interrupt masked 1 = interrupt enabled Bit 2 / Receive Alarm Indication Signal Condition Detect (RAISD) 0 = interrupt masked 1 = interrupt enabled Bit 3 / Receive Remote Alarm Indication Condition Detect (RRAID) 0 = interrupt masked 1 = interrupt enabled Bit 4 / Receive Loss-of-Frame Condition Clear (RLOFC) 0 = interrupt masked 1 = interrupt enabled Bit 5 / Receive Loss-of-Signal Condition Clear (RLOSC) 0 = interrupt masked 1 = interrupt enabled Bit 6 / Receive Alarm Indication Signal Condition Clear (RAISC) 0 = interrupt masked 1 = interrupt enabled Bit 7 / Receive Remote Alarm Indication Condition Clear (RRAIC) 0 = interrupt masked 1 = interrupt enabled 55 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 RPDV 0 RLS2 Receive Latched Status Register 2 091h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 COFA 0 4 8ZD 0 3 16ZD 0 2 SEFE 0 1 B8ZS 0 0 FBE 0 All bits in this register are latched. This register does not create interrupts. Bit 0 / Frame Bit Error Event (FBE). Set when an Ft (D4) or FPS (ESF) framing bit is received in error. Bit 1 / B8ZS Codeword Detect Event (B8ZS). Set when a B8ZS codeword is detected at RPOS and RNEG independent of whether the B8ZS mode is selected or not. This bit is useful for automatically setting the line coding. Bit 2 / Severely Errored Framing Event (SEFE). Set when 2 out of 6 framing bits (Ft or FPS) are received in error. Bit 3 / Sixteen Zero Detect Event (16ZD). Set when a string of at least 16 consecutive zeros (regardless of the length of the string) have been received at RPOS and RNEG. Bit 4 / Eight Zero Detect Event (8ZD). Set when a string of at least eight consecutive zeros (regardless of the length of the string) have been received at RPOS and RNEG. Bit 5 / Change-of-Frame Alignment Event (COFA). Set when the last resync resulted in a change of frame or multiframe alignment. Bit 6 / Unused Bit 7 / Receive Pulse Density Violation Event (RPDV). Set when the receive data stream does not meet the ANSI T1.403 requirements for pulse density. Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 RRTS3 Receive Real-Time Status Register 3 0B2h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 -- 0 4 -- 0 3 LORC 0 2 LSP 0 1 LDN 0 0 LUP 0 All bits in this register are real-time (not latched). Bit 0 / Loop-Up Code Detected Condition (LUP). Set when the loop-up code as defined in the RUPCD1/2 register is being received. Bit 1 / Loop-Down Code Detected Condition (LDN). Set when the loop-down code as defined in the RDNCD1/2 register is being received. Bit 2 / Spare Code Detected Condition (LSP). Set when the spare code as defined in the RSCD1/2 registers is being received. Bit 3 / Loss-of-Receive Clock Condition (LORC). Set when the RCLK pin has not transitioned for one channel time. Bits 4 to 7 / Unused 56 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: RLS3 Receive Latched Status Register 3 092h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 Bit # Name Default 7 LORCC 0 6 LSPC 0 5 LDNC 0 4 LUPC 0 3 LORCD 0 2 LSPD 0 1 LDND 0 0 LUPD 0 All bits in this register are latched and can create interrupts. Bit 0 / Loop-Up Code Detected Condition Detect (LUPD). Rising edge detect of LUP. Set when the loop-up code as defined in the RUPCD1/2 register is being received. Bit 1 / Loop-Down Code Detected Condition Detect (LDND). Rising edge detect of LDN. Set when the loopdown code as defined in the RDNCD1/2 register is being received. Bit 2 / Spare Code Detected Condition Detect (LSPD). Rising edge detect of LSP. Set when the spare code as defined in the RSCD1/2 registers is being received. Bit 3 / Loss of Receive Clock Condition Detect (LORCD). Rising edge detect of LORC. Set when the RCLK pin has not transitioned for one channel time. Bit 4 / Loop-Up Code Detected Condition Clear (LUPC). Falling edge detect of LUP. Set when a loop-up condition was detected and then removed. Bit 5 / Loop-Down Code Detected Condition Clear (LDNC). Falling edge detect of LDN. Set when a loop-down condition was detected and then removed. Bit 6 / Spare Code Detected Condition Clear (LSPC). Falling edge detect of LSP. Set when a spare-code match condition was detected and then removed. Bit 7 / Loss-of-Receive Clock Condition Clear (LORCC). Falling edge detect of LORC. Set when a LORC condition was detected and then removed. 57 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 LORCC 0 RIM3 Receive Interrupt Mask Register 3 0A2h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 LSPC 0 5 LDNC 0 4 LUPC 0 3 LORCD 0 2 LSPD 0 1 LDND 0 0 LUPD 0 Bit 0 / Loop-Up Code Detected Condition Detect (LUPD) 0 = interrupt masked 1 = interrupt enabled Bit 1 / Loop-Down Code Detected Condition Detect (LDND) 0 = interrupt masked 1 = interrupt enabled Bit 2 / Spare Code Detected Condition Detect (LSPD) 0 = interrupt masked 1 = interrupt enabled Bit 3 / Loss-of-Receive Clock Condition Detect (LORCD) 0 = interrupt masked 1 = interrupt enabled Bit 4 / Loop-Up Code Detected Condition Clear (LUPC) 0 = interrupt masked 1 = interrupt enabled Bit 5 / Loop-Down Code Detected Condition Clear (LDNC) 0 = interrupt masked 1 = interrupt enabled Bit 6 / Spare Code Detected Condition Clear (LSPC) 0 = interrupt masked 1 = interrupt enabled Bit 7 / Loss-of-Receive Clock Condition Clear (LORCC) 0 = interrupt masked 1 = interrupt enabled 58 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 RESF 0 RLS4 Receive Latched Status Register 4 093h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 RESEM 0 5 RSLIP 0 4 -- 0 3 RSCOS 0 2 1SEC 0 1 TIMER 0 0 RMF 0 All bits in this register are latched and can create interrupts. Bit 0 / Receive Multiframe Event (RMF). Set every 1.5ms on D4 MF boundaries or every 3ms on ESF MF boundaries. Bit 1 / Timer Event (TIMER). Follows the error counter update interval as determined by the ECUS bit in the error counter configuration register (ERCNT). T1: Set on increments of 1 second or 42ms based on RCLK. E1: Set on increments of 1 second or 62.5ms based on RCLK. Bit 2 / One-Second Timer (1SEC). Set on every one-second interval based on RCLK. Bit 3 / Receive Signaling Change-of-State Event (RSCOS). Set when any channel selected by the receive signaling change-of-state interrupt-enable registers (RSCSE1 through RSCSE3), changes signaling state. Bit 4 / Unused Bit 5 / Receive Elastic Store Slip Occurrence Event (RSLIP). Set when the receive-elastic store has either repeated or deleted a frame. Bit 6 / Receive Elastic Store Empty Event (RESEM). Set when the receive-elastic store buffer empties and a frame is repeated. Bit 7 / Receive Elastic Store Full Event (RESF). Set when the receive-elastic store buffer fills and a frame is deleted. 59 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 RESF 0 RIM4 Receive Interrupt Mask Register 4 0A3h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 RESEM 0 5 RSLIP 0 4 -- 0 3 RSCOS 0 2 1SEC 0 1 TIMER 0 0 RMF 0 Bit 0 / Receive Multiframe Event (RMF) 0 = interrupt masked 1 = interrupt enabled Bit 1 / Timer Event (TIMER) 0 = interrupt masked 1 = interrupt enabled Bit 2 / One-Second Timer (1SEC) 0 = interrupt masked 1 = interrupt enabled Bit 3 / Receive Signaling Change-of-State Event (RSCOS) 0 = interrupt masked 1 = interrupt enabled Bit 4 / Unused. Must be set = 0 for proper operation. Bit 5 / Receive Elastic Store Slip Occurrence Event (RSLIP) 0 = interrupt masked 1 = interrupt enabled Bit 6 / Receive Elastic Store Empty Event (RESEM) 0 = interrupt masked 1 = interrupt enabled Bit 7 / Receive Elastic Store Full Event (RESF) 0 = interrupt masked 1 = interrupt enabled 60 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 RLS7 Receive Latched Status Register 7 096h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 RRAI-CI 0 4 RAIS-CI 0 3 RSLC96 0 2 RFDLF 0 1 BC 0 0 BD 0 All bits in this register are latched and can create interrupts. Bit 0 / BOC Detect Event (BD). Set when a valid BOC has been detected (with the BOC filter applied) (Section 11.11) Bit 1 / BOC Clear Event (BC). Set when a valid BOC is no longer detected (with the disintegration filter applied). (Section 11.11) Bit 2 / Receive FDL Register Full Event (RFDLF). Set when the 8-bit RFDL register is full. Useful for SLC-96 operation, or manual extraction of FDL data bits (Sections 11.12 and 11.13). Bit 3 / Receive SLC-96 Alignment Event (RSLC96). Set when a valid SLC-96 alignment pattern is detected in the fs-bit stream, and the RSLCx registers have data available for retrieval (Section 11.12). Bit 4 / Receive AIS-CI Detect (RAIS-CI). Set when an AIS-CI pattern has been detected by the receiver (see Section 11.5.1). This bit is set only if an AIS condition is being detected (RRTS1.2). This is a latched bit that must be cleared by the host, and sets again each time the AIS-CI pattern is detected (approximately every 1.2 seconds). Bit 5 / Receive RAI-CI Detect (RRAI-CI). Set when an RAI-CI pattern has been detected by the receiver (see Section 11.5.1). This bit is active in ESF-framing mode only, and sets only if an RAI condition is being detected (RRTS1.3). When the host reads (and clears) this bit, it will set again each time the RAI-CI pattern is detected (approximately every 1.1 seconds). Bits 6, 7 / Unused 61 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 RIM7 Receive Interrupt Mask Register 7 (BOC/FDL) A6h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 RRAI-CI 0 4 RAIS-CI 0 3 RSLC96 0 2 RFDLF 0 1 BC 0 0 BD 0 Bit 0 / BOC Detect Event (BD) 0 = interrupt masked 1 = interrupt enabled Bit 1 / BOC Clear Event (BC) 0 = interrupt masked 1 = interrupt enabled Bit 2 / Receive FDL Register Full (RFDLF) 0 = interrupt masked 1 = interrupt enabled Bit 3 / Receive SLC-96 (RSLC96) 0 = interrupt masked 1 = interrupt enabled Bit 4 / Receive AIS-CI (RAIS-CI) 0 = interrupt masked 1 = interrupt enabled Bit 5 / Receive RAI-CI (RRAI-CI) 0 = interrupt masked 1 = interrupt enabled Bits 6, 7 / Unused. Must be set = 0 for proper operation. 62 DS26401 Octal T1/E1/J1 Framer 8.7.1 Receive AIS-CI and RAI-CI Detection AIS-CI is a repetitive pattern of 1.26 seconds. It consists of 1.11 seconds of an unframed all ones pattern and 0.15 seconds of all ones modified by the AIS-CI signature. The AIS-CI signature is a repetitive pattern 6176 bits in length in which, if the first bit is numbered bit 0, bits 3088, 3474 and 5790 are logical zeros and all other bits in the pattern are logical ones (T1.403). AIS-CI is an unframed pattern and therefore is defined for all T1 framing formats. The RAIS-CI bit is set when the AIS-CI pattern has been detected and RAIS (RRTS1.2) is set. RAIS-CI is a latched bit and should be cleared by the host when read. RAIS-CI will continue to set approximately every 1.2 seconds that the condition is present. The host will need to `poll' the bit, in conjunction with the normal AIS indicators to determine when the condition has cleared. RAI-CI is a repetitive pattern within the ESF data link with a period of 1.08 seconds. It consists of sequentially interleaving 0.99 seconds of "00000000 11111111" (right-to-left) with 90ms of "00111110 11111111". The RRAI-CI bit is set when a bit-oriented code of "00111110 11111111" is detected while RRAI (RRTS1.3) is set. The RRAI-CI detector uses the receive BOC filter bits (RBF0 & RBF1) located in RBOCC to determine the integration time for RAI-CI detection. Like RAIS-CI, the RRAI-CI bit is latched and should be cleared by the host when read. RRAI-CI will continue to set approximately every 1.1 seconds that the condition is present. The host will need to `poll' the bit, in conjunction with the normal RAI indicators to determine when the condition has cleared. It may be useful to enable the 200ms ESF RAI integration time with the RAIIE control bit (RCR2.1) in networks that use RAI-CI. 8.8 T1 Receive-Side Digital Milliwatt Code Generation Receive-side digital milliwatt code generation involves using the receive-digital milliwatt registers (T1RDMR1/2/3) to determine which of the 24 T1 channels of the T1 line going to the backplane should be overwritten with a digital milliwatt pattern. The digital milliwatt code is an 8-byte repeating pattern that represents a 1kHz sine wave (1E/0B/0B/1E/9E/8B/8B/9E). Each bit in the T1RDMRx registers, represents a particular channel. If a bit is set to 1, then the receive data in that channel is replaced with the digital milliwatt code. If a bit is set to zero, no replacement occurs. Register Name: Register Description: Register Address: (MSB) CH8 CH16 CH24 RDMWE1, RDMWE2, RDMWE3 T1 Receive-Digital Milliwatt-Enable Registers 03Ch, 03Dh, 03Eh [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8] (LSB) CH1 CH9 CH17 CH7 CH15 CH23 CH6 CH14 CH22 CH5 CH13 CH21 CH4 CH12 CH20 CH3 CH11 CH19 CH2 CH10 CH18 RDMWE1 RDMWE2 RDMWE3 Bits 0 to 7 / Receive-Digital Milliwatt Enable for Channels 1 to 24 (CH1 to CH24) 0 = Do not affect the receive data associated with this channel. 1 = Replace the receive data associated with this channel with digital milliwatt code. 63 DS26401 Octal T1/E1/J1 Framer 8.9 T1 Error Count Registers The DS26401 contains three T1 performance counters that are used to accumulate line coding errors, path errors, and synchronization errors. Counter update options include one-second boundaries, 42ms (T1 mode only), 62.5ms (E1 mode only), or manually. See the Error Counter Configuration Register (ERCNT) section. When updated automatically, the user can use the interrupt from the timer to determine when to read these registers. The line-code violation count register has the potential to saturate, but the bit error would have to exceed 10E-2 before this would occur. All other counters roll over. Several options are available for latching the performance counters: 1) Each framer's counters are latched independently based on independent one-second interval timers. 2) Each framer's counters are latched independently based on independent 42ms interval timers. 3) Each framer's counters are latched independently with a low-to-high transition on the respective MECU control bit. 4) Counters from selected framers are latched synchronously at the one-second interval supplied by Framer #1. 5) Counters from selected framers are synchronously latched manually with the global counter latch-enable (GCLE) bit in GCR1. The following table shows control bit settings in the ERCNT register to support each of the five modes discussed above. Control Bit EAMS ECUS MECU MCUS 1SECS Mode 1 0 0 0 0 0 Mode 2 0 1 0 0 0 Mode 3 1 X 0 to 1 0 0 Mode 4 0 0 0 0 1 Mode 5 1 0 0 1 0 64 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 1SECS 0 ERCNT Error Counter Configuration Register 086h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 MCUS 0 5 MECU 0 4 ECUS 0 3 EAMS 0 2 FSBE 0 1 MOSCRF 0 0 LCVCRF 0 Bit 0 / T1 Line-Code Violation Count Register Function Select (LCVCRF) 0 = do not count excessive zeros 1 = count excessive zeros Bit 1 / Multiframe Out-of-Sync Count Register Function Select (MOSCRF) 0 = count errors in the framing bit position 1 = count the number of out-of-sync multiframes Bit 2 / PCVCR Fs-Bit Error Report Enable (FSBE) 0 = do not report bit errors in Fs-bit position; only Ft bit position 1 = report bit errors in Fs-bit position as well as Ft bit position Bit 3 / Error Accumulation Mode Select (EAMS) 0 = ERCNT.4 determines accumulation time (timed update) 1 = ERCNT.5 determines accumulation time (manual update) Bit 4 / Error Counter Update Select (ECUS) T1 mode: 0 = Update error counters once a second 1 = Update error counters every 42ms (336 frames) E1 mode: 0 = Update error counters once a second 1 = Update error counters every 62.5ms (500 frames) Bit 5 / Manual Error Counter Update (MECU). When enabled by ERCNT.3, the changing of this bit from 0 to 1 allows the next clock cycle to load the error counter registers with the latest counts and reset the counters. The user must wait a minimum of 250ms before reading the error count registers to allow for proper update. Bit 6 / Manual Counter Update Select (MCUS). When manual update mode is enabled with EAMS, this bit can be used to allow the GLCE bit in GCR1 to latch all counters. Useful for synchronously latching counters of multiple framers. 0 = MECU is used to manually latch counters. 1 = GLCE is used to manually latch counters. Bit 7 / One-Second Select (1SECS). When timed update is enabled by EAMS, setting this bit for a specific framer allows that framer's counters to latch on the one-second reference from Framer #1. 0 = Use internally generated one-second timer. 1 = Use one-second timer from Framer #1. 65 DS26401 Octal T1/E1/J1 Framer 8.9.1 T1 Line-Code Violation Count Register (LCVCR) T1 code violations are defined as bipolar violations (BPVs) or excessive zeros. If the B8ZS mode is set for the receive side, then B8ZS codewords are not counted. This counter is always enabled; it is not disabled during receive loss-of-synchronization (RLOF = 1) conditions. See Table 8-2 for details of exactly what the LCVCRs count. Table 8-2. T1 Line-Code Violation Counting Options COUNT EXCESSIVE ZEROS? (ERCNT.0) No Yes No Yes B8ZS ENABLED? (RCR1.6) No No Yes Yes WHAT IS COUNTED IN THE LCVCRs BPVs BPVs + 16 consecutive zeros BPVs (B8ZS codewords not counted) BPVs + 8 consecutive zeros Register Name: Register Description: Register Address: Bit # Name Default 7 LCVC15 0 LCVCR1 Line-Code Violation Count Register 1 050h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 LCVC14 0 5 LCVC13 0 4 LCVC12 0 3 LCVC11 0 2 LCVC10 0 1 LCVC9 0 0 LCCV8 0 Bits 0 to 7 / Line-Code Violation Counter Bits 8 to 15 (LCVC8 to LCVC15). LCV15 is the MSB of the 16-bit code violation count. Register Name: Register Description: Register Address: Bit # Name Default 7 LCVC7 0 LCVCR2 Line-Code Violation Count Register 2 051h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 LCVC6 0 5 LCVC5 0 4 LCVC4 0 3 LCVC3 0 2 LCVC2 0 1 LCVC1 0 0 LCVC0 0 Bits 0 to 7 / Line-Code Violation Counter Bits 0 to 7 (LCVC0 to LCVC7). LCV0 is the LSB of the 16-bit code violation count 66 DS26401 Octal T1/E1/J1 Framer 8.9.2 T1 Path-Code Violation Count Register (PCVCR) The path-code violation count register records either Ft, Fs, or CRC6 errors in T1 frames. When the receive side of a framer is set to operate in the T1 ESF framing mode, PCVCR records errors in the CRC6 codewords. When set to operate in the T1 D4 framing mode, PCVCR counts errors in the Ft framing bit position. Through the ERCNT.2 bit, a framer can be programmed to also report errors in the Fs framing bit position. The PCVCR is disabled during receive loss-of-synchronization (RLOF = 1) conditions. See Table 8-3 for a detailed description of exactly what errors the PCVCR counts. Table 8-3. T1 Path-Code Violation Counting Arrangements FRAMING MODE D4 D4 ESF COUNT Fs ERRORS? No Yes Don't Care WHAT IS COUNTED IN THE PCVCRs Errors in the Ft pattern Errors in both the Ft & Fs patterns Errors in the CRC6 codewords Register Name: Register Description: Register Address: Bit # Name Default 7 PCVC15 0 PCVCR1 Path-Code Violation Count Register 1 052h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 PCVC14 0 5 PCVC13 0 4 PCVC12 0 3 PCVC11 0 2 PCVC10 0 1 PCVC9 0 0 PCVC8 0 Bits 0 to 7 / Path-Code Violation Counter Bits 8 to 15 (PCVC8 to PCVC15). PCVC15 is the MSB of the 16-bit path-code violation count Register Name: Register Description: Register Address: Bit # Name Default 7 PCVC7 0 PCVCR2 Path-Code Violation Count Register 2 053h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 PCVC6 0 5 PCVC5 0 4 PCVC4 0 3 PCVC3 0 2 PCVC2 0 1 PCVC1 0 0 PCVC0 0 Bits 0 to 7 / Path-Code Violation Counter Bits 0 to 7 (PCVC0 to PCVC7). PCVC0 is the LSB of the 16-bit pathcode violation count. 67 DS26401 Octal T1/E1/J1 Framer 8.9.3 T1 Frames Out-of-Sync Count Register (FOSCR) The FOSCR is used to count the number of multiframes that the receive synchronizer is out of sync. This number is useful in ESF applications needing to measure the parameters loss-of-frame count (LOFC) and ESF error events as described in AT&T publication TR54016. When the FOSCR is operated in this mode, it is not disabled during receive loss of synchronization (RLOF = 1) conditions. The FOSCR has alternate operating mode whereby it will count either errors in the Ft framing pattern (in the D4 mode) or errors in the FPS framing pattern (in the ESF mode). When the FOSCR is operated in this mode, it is disabled during receive loss-of-synchronization (RLOF = 1) conditions. See Table 8-4 for a detailed description of what the FOSCR is capable of counting. Table 8-4. T1 Frames Out-of-Sync Counting Arrangements FRAMING MODE (RCR1.5) D4 D4 ESF ESF COUNT MOS OR F-BIT ERRORS (ERCNT.1) MOS F-Bit MOS F-Bit WHAT IS COUNTED IN THE FOSCRs Number of multiframes out of sync Errors in the Ft pattern Number of multiframes out of sync Errors in the FPS pattern Register Name: Register Description: Register Address: Bit # Name Default 7 FOS15 0 FOSCR1 Frames Out-of-Sync Count Register 1 054h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 FOS14 0 5 FOS13 0 4 FOS12 0 3 FOS11 0 2 FOS10 0 1 FOS9 0 0 FOS8 0 Bits 0 to 7 / Frames Out-of-Sync Counter Bits 8 to 15 (FOS8 to FOS15). FOS15 is the MSB of the 16-bit frames out-of-sync count. Register Name: Register Description: Register Address: Bit # Name Default 7 FOS7 0 FOSCR2 Frames Out-of-Sync Count Register 2 055h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 FOS6 0 5 FOS5 0 4 FOS4 0 3 FOS3 0 2 FOS2 0 1 FOS1 0 0 FOS0 0 Bits 0 to 7 / Frames Out-of-Sync Counter Bits 0 to 7 (FOS0 to FOS7). FOS0 is the LSB of the 16-bit frames outof-sync count. 68 DS26401 Octal T1/E1/J1 Framer 8.10 DS0 Monitoring Function The DS26401 can monitor one DS0 (64kbps) channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the receive direction, the RCM0 to RCM4 bits in the RDS0SEL register need to be properly set and the DS0 channel pointed to by the RCM0 to RCM4 bits will appear in the receive DS0 (RDS0M) register. The RCM4 to RCM0 bits should be programmed with the decimal decode of the appropriate T1 channel. T1 channels 1 through 24 map to register values 0 through 23. For example, if DS0 channel 15 in the receive direction needed to be monitored, then the following values would be programmed into RDS0SEL: RCM4 = 0 RCM3 = 1 RCM2 = 1 RCM1 = 1 RCM0 = 0 Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 RDS0SEL Receive-Channel Monitor Select 012h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 -- 0 4 RCM4 0 3 RCM3 0 2 RCM2 0 1 RCM1 0 0 RCM0 0 Bits 0 to 4 / Receive-Channel Monitor Bits (RCM0 to RCM4). RCM0 is the LSB of a 5-bit channel select that determines which receive-DS0 channel data appears in the RDS0M register. Bits 5-7 / Unused. Must be set = 0 for proper operation. Register Name: Register Description: Register Address: Bit # Name Default 7 B1 0 RDS0M Receive-DS0 Monitor Register 060h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 B2 0 5 B3 0 4 B4 0 3 B5 0 2 B6 0 1 B7 0 0 B8 0 Bits 0 to 7 / Receive-DS0 Channel Bits (B1 to B8). Receive-channel data that has been selected by the receivechannel monitor select register. B8 is the LSB of the DS0 channel (last bit to be received). 69 DS26401 Octal T1/E1/J1 Framer 8.11 T1 Receive Signaling Operation There are two methods to access receive-signaling data: through processor-based (i.e., software-based) signaling or hardware-based signaling. Processor-based refers to access through the receive-signaling registers, RS1-RS12. Hardware-based refers to the RSIG pin. Both methods can be used simultaneously. 8.11.1 Processor-Based Signaling The robbed-bit signalingis sampled in the receive data stream and copied into the receive-signaling registers, RS1 through RS12. The signaling information in these registers is always updated on multiframe boundaries. This function is always enabled. 8.11.2 Change of State To avoid constant monitoring of the receive-signaling registers, the DS26401 can be programmed to alert the host when any specific channel or channels undergo a change of their signaling state. For T1, RSCSE1 through RSCSE3 are used to select which channels can cause a change-of-state indication. The change of state is indicated in latched status register 4 (RLS4.3). If signaling integration is enabled, the new signaling state must be constant for three multiframes before a change-of-state indication is indicated. The user can enable the INT pin to toggle low upon detection of a change in signaling by setting the interrupt mask bit RIM4.3. The signaling integration mode is global and cannot be enabled on a channel-by-channel basis. The user can identify which channels have undergone a signaling change of state by reading the receive-signaling status (RSS1-RSS3) registers. The information from these registers tells the user which RSx register to read for the new signaling data. All changes are indicated in the RSS1-RSS3 registers regardless of the RSCSE1-RSCSE3 registers. 8.11.3 Hardware-Based Receive Signaling In hardware-based signaling, the signaling data can be obtained from the RSER pin or the RSIG pin. RSIG is a signaling-PCM stream output on a channel-by-channel basis from the signaling buffer. The T1 robbed-bit signaling data is still present in the original data stream at RSER. The signaling buffer provides signaling data to the RSIG pin and also allows signaling data to be reinserted into the original data stream in a different alignment that is determined by a multiframe signal from the RSYNC pin. In this mode, the receive-elastic store can be enabled or disabled. If the receive-elastic store is enabled, then the backplane clock (RSYSCLK) can be either 1.544MHz or 2.048MHz. If IBO mode is enabled, then RSYSCLK can also be 4.096MHz, 8.192MHz, or 16.384MHz. In the ESFframing mode, the ABCD signaling bits are output on RSIG in the lower nibble of each channel. The RSIG data is updated once a multiframe (3ms) unless a freeze is in effect. In the D4 framing mode, the AB signaling bits are output twice on RSIG in the lower nibble of each channel. Hence, bits 5 and 6 contain the same data as bits 7 and 8, respectively, in each channel. The RSIG data is updated once a multiframe (1.5ms) unless a freeze is in effect. 8.11.4 Signaling Debounce When signaling integration is enabled, the signaling data at RSIG is automatically debounced. Signaling must be constant for three multiframes before being updated at RSIG. Signaling debounce is enabled on a global basis. 70 DS26401 Octal T1/E1/J1 Framer 8.11.5 Receive-Signaling Reinsertion at RSER In this mode, the user provides a multiframe sync at the RSYNC pin, and the signaling data is reinserted based on this alignment. In T1 mode, this results in two copies of the signaling data in the RSER data stream. The original signaling data is based on the Fs/ESF frame positions and the realigned data is based on the user-supplied multiframe sync applied at RSYNC. In voice channels, this extra copy of signaling data is of little consequence. Reinsertion can be avoided in data channels since this feature is activated on a per-channel basis. For reinsertion, the elastic store must be enabled, however, the backplane clock can be either 1.544MHz or 2.048MHz. Signaling reinsertion mode is enabled on a per-channel basis by setting the receive-signaling reinsertion channelselect bit high in the RSIx registers. The channels that are to have signaling reinserted are selected by writing to the RSI1-RSI3 registers for T1. 8.11.6 Force Receive-Signaling All Ones In T1 mode, the user can, on a per-channel basis, force the robbed-bit signaling bit positions to 1. This is done by using the RSAOI registers. The user sets the channel-select bit in the RSAOI1-RSAOI3 registers to select the channels that are to have the signaling forced to 1. 8.11.7 Receive-Signaling Freeze The signaling data in the four-multiframe signaling buffer is frozen in a known good state upon either a loss-ofsynchronization (OOF event), carrier loss, or change-of-frame alignment. This action meets the requirements of BellCore TR-TSY-000170 for signaling freezing. To allow this freeze action to occur, the RSFE control bit (RSIGC.1) should be set high. The user can force a freeze by setting the RSFF control bit (RSIGC.2) high. The RSIGF output pin provides a hardware indication that a freeze is in effect. The four-multiframe buffer provides a three-multiframe delay in the signaling bits provided at the RSIG pin (and at the RSER pin if receive-signaling reinsertion is enabled). When freezing is enabled (RSFE = 1), the signaling data is held in the last known good state until the corrupting error condition subsides. When the error condition subsides, the signaling data is held in the old state for at least an additional 9ms (or 4.5ms in D4 framing mode) before being allowed to be updated with new signaling data. 71 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 RSIGC Receive Signaling Control Register 013h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 -- 0 4 RFSA1 0 3 -- 0 2 RSFF 0 1 RSFE 0 0 RSIE 0 Bit 0 / Receive-Signaling Integration Enable (RSIE) 0 = signaling changes of state reported on any change in selected channels 1 = signaling must be stable for three multiframes for a change of state to be reported Bit 1 / Receive-Signaling Freeze Enable (RSFE) 0 = no freezing of receive-signaling data occurs 1 = allow freezing of receive-signaling data at RSIG (and RSER if receive-signaling reinsertion is enabled) Bit 2 / Receive-Signaling Force Freeze (RSFF). Freezes receive-side signaling at RSIG (and RSER if receivesignaling reinsertion is enabled); overrides receive-freeze enable (RFE). 0 = do not force a freeze event 1 = force a freeze event Bits 3, 5-7 / Unused. Must be set = 0 for proper operation. Bit 4 / Receive-Force Signaling All Ones (RFSA1) 0 = do not force robbed bit signaling to all ones 1 = force signaling bits to all ones on a per-channel basis according to the RSAOI1-RSAOI3 registers 72 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: RS1 to RS12 Receive Signaling Registers 040h to 04Bh [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8] In the ESF framing mode, there can be up to four signaling bits per channel (A, B, C, and D). In the D4 framing mode, there are only two signaling bits per channel (A and B). In the D4 framing mode, the framer repeats the A and B signaling data in the C and D bit locations. Therefore, when the framer is operated in D4 framing mode, the user needs to retrieve the signaling bits every 1.5ms as opposed to 3ms for ESF mode. The receive-signaling registers are frozen and not updated during a loss-of-sync condition. They contain the most recent signaling information before the OOF occurred. (MSB) CH1-A CH2-A CH3-A CH4-A CH5-A CH6-A CH7-A CH8-A CH9-A CH10-A CH11-A CH12-A (LSB) CH13-D CH14-D CH15-D CH16-D CH17-D CH18-D CH19-D CH20-D CH21-D CH22-D CH23-D CH24-D CH1-B CH2-B CH3-B CH4-B CH5-B CH6-B CH7-B CH8-B CH9-B CH10-B CH11-B CH12-B CH1-C CH2-C CH3-C CH4-C CH5-C CH6-C CH7-C CH8-C CH9-C CH10-C CH11-C CH12-C CH1-D CH2-D CH3-D CH4-D CH5-D CH6-D CH7-D CH8-D CH9-D CH10-D CH11-D CH12-D CH13-A CH14-A CH15-A CH16-A CH17-A CH18-A CH19-A CH20-A CH21-A CH22-A CH23-A CH24-A CH13-B CH14-B CH15-B CH16-B CH17-B CH18-B CH19-B CH20-B CH21-B CH22-B CH23-B CH24-B CH13-C CH14-C CH15-C CH16-C CH17-C CH18-C CH19-C CH20-C CH21-C CH22-C CH23-C CH24-C RS1 RS2 RS3 RS4 RS5 RS6 RS7 RS8 RS9 RS10 RS11 RS12 73 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: RSS1, RSS2, RSS3 Receive Signaling Status Registers 098h, 099h, 09Ah [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8] When a channel's signaling data changes state, the respective bit in registers RSS1-RSS3 is set and latched. The RSCOS bit (RLSR4.3) is set if the channel was also enabled by setting the appropriate bit in RSCSE1-3. The INT signal goes low if enabled by the interrupt mask bit RIM4.3. (MSB) CH8 CH16 CH24 (LSB) CH1 CH9 CH17 CH7 CH15 CH23 CH6 CH14 CH22 CH5 CH13 CH21 CH4 CH12 CH20 CH3 CH11 CH19 CH2 CH10 CH18 RSS1 RSS2 RSS3 Note: Status bits in this register are latched. Register Name: Register Description: Register Address: RSCSE1, RSCSE2, RSCSE3 Receive-Signaling Change-of-State Enable 0A8h, 0A9h, 0AAh [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8] Setting any of the CH1 through CH24 bits in the RSS1 through RSS3 registers cause RSCOS (RLSR4.3) to be set when that channel's signaling data changes state. (MSB) CH8 CH16 CH24 (LSB) CH1 CH9 CH17 CH7 CH15 CH23 CH6 CH14 CH22 CH5 CH13 CH21 CH4 CH12 CH20 CH3 CH11 CH19 CH2 CH10 CH18 RSCSE1 RSCSE2 RSCSE3 74 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: RSI1, RSI2, RSI3, RSI4 Receive-Signaling Reinsertion Enable Registers 0C8h, 0C9h, 0CAh, 0CBh [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8] Setting any of the CH1 through CH24 bits in the RSI1 through RSI3 registers causes signaling data to be reinserted for the associated channel. RSI4 is used for 2.048MHz backplane operation. (MSB) CH8 CH16 CH24 CH32 (LSB) CH1 CH9 CH17 CH25 CH7 CH15 CH23 CH31 CH6 CH14 CH22 CH30 CH5 CH13 CH21 CH29 CH4 CH12 CH20 CH28 CH3 CH11 CH19 CH27 CH2 CH10 CH18 CH26 RSI1 RSI2 RSI3 RSI4* Register Name: Register Description: Register Address: RSAOI1, RSAOI2, RSAOI3, Receive-Signaling All-Ones Insertion Registers 038h, 039h, 03Ah [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8] Setting any of the CH1 through CH24 bits in the RSAOI1 through RSAOI3 registers causes signaling data to be replaced with logic ones as received at the backplane. (MSB) CH8 CH16 CH24 (LSB) CH1 CH9 CH17 CH7 CH15 CH23 CH6 CH14 CH22 CH5 CH13 CH21 CH4 CH12 CH20 CH3 CH11 CH19 CH2 CH10 CH18 RSAOI1 RSAOI2 RSAOI3 75 DS26401 Octal T1/E1/J1 Framer 8.12 T1 Receive Per-Channel Idle Code Insertion Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions. Twenty-four receive idle definition registers (RIDR1-RIDR24) are provided to set the 8-bit idle code for each channel. The receive-channel idle code-enable registers (RCICE1-3) are used to enable idle code replacement on a per-channel basis. Register Name: Register Description: Register Address: Bit # Name Default 7 C7 0 RIDR1 to RIDR24 Receive Idle-Code Definition Registers 1 to 24 020h to 037h [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8] 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Bits 0 to 7 / Per-Channel Idle Code Bits (C0 to C7). C0 is the LSB of the code (this bit is transmitted last). Address 20H is for channel 1; address 37H is for channel 24. Register Name: Register Description: Register Address: RCICE1, RCICE2, RCICE3 Receive-Channel Idle Code-Enable Registers 0D0h, 0D1h, 0D2h [+ (200h * n) : where n = 0 to 7, for Ports 1 to 8] The receive-channel idle code-enable registers (RCICE1/2/3) are used to determine which of the 24 T1 channels from the T1 line to the backplane should be overwritten with the code placed in the receive idle-code definition register. (MSB) CH8 CH16 CH24 (LSB) CH1 CH9 CH17 CH7 CH15 CH23 CH6 CH14 CH22 CH5 CH13 CH21 CH4 CH12 CH20 CH3 CH11 CH19 CH2 CH10 CH18 RCICE1 RCICE2 RCICE3 Bits 0 to 7 / Receive Channels 1 to 24 Code Insertion Control Bits (CH1 to CH24) 0 = do not insert data from the idle code array into the receive data stream 1 = insert data from the idle code array into the receive data stream 76 DS26401 Octal T1/E1/J1 Framer 8.13 Receive-Channel Blocking Operation The receive-channel blocking registers (RCBR1/RCBR2/RCBR3/RCBR4) and the transmit-channel blocking registers (TCBR1/TCBR2/TCBR3/TCBR4) control the RCHBLK and TCHBLK pins respectively. The RCHBLK and TCHBLK pins are user-programmable outputs that can be forced high or low during individual channels. These outputs can be used to block clocks to a USART or LAPD controller in ISDN-PRI applications. When the appropriate bits are set to 1, the RCHBLK and TCHBLK pin is held high during the entire corresponding channel time. When used in T1 mode, only RCBR1 to RCBR3 and the LSB of RCBR4 are used. Register Name: Register Description: Register Address: RCBR1, RCBR2, RCBR3, RCBR4 Receive-Channel Blocking Registers 0C4h, 0C5h, 0C6h, 0C7h [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8] (LSB) CH1 CH9 CH17 CH25/Fbit (MSB) CH8 CH16 CH24 CH32 CH7 CH15 CH23 CH31 CH6 CH14 CH22 CH30 CH5 CH13 CH21 CH29 CH4 CH12 CH20 CH28 CH3 CH11 CH19 CH27 CH2 CH10 CH18 CH26 RCBR1 RCBR2 RCBR3 RCBR4* Bits 0 to 7 / Receive Channels 1 to 32 Channel Blocking Control Bits (CH1 to CH32). 0 = force the RCHBLK pin to remain low during this channel time 1 = force the RCHBLK pin high during this channel time In T1 mode, the LSB of RCBR4 determines whether or not the RCHBLK signal pulses high during the F-bit time: RCBR4.0 = 0, do not pulse RCHBLK during the F-bit RCBR4.0 = 1, pulse RCHBLK during the F-bit In this mode RCBR4.1 to RCBR4.7 should be set to 0. 77 DS26401 Octal T1/E1/J1 Framer 8.14 Receive Elastic Stores Operation The DS26401 contains dual, two-frame elastic stores--one for the receive direction and one for the transmit direction. Both elastic stores are fully independent. The transmit- and receive-side elastic stores can be enabled/disabled independent of each other. Also, each elastic store can interface to either a 1.544MHz or 2.048MHz/4.096MHz/8.192MHz/16.384MHz backplane without regard to the backplane rate for the other elastic store. The elastic stores have two main purposes. First, they can be used for rate conversion. When the DS26401 is in the T1 mode, the elastic stores can rate-convert the T1 data stream to a 2.048MHz backplane. In E1 mode, the elastic store can rate-convert the E1 data stream to a 1.544MHz backplane. Secondly, they can be used to absorb the differences in frequency and phase between the T1 or E1 data stream and an asynchronous (i.e., not locked) backplane clock (which can be 1.544MHz or 2.048MHz). In this mode, the elastic stores manage the rate difference and perform controlled slips, deleting or repeating frames of data in order to manage the difference between the network and the backplane. The elastic stores can also be used to multiplex T1 or E1 data streams into higher backplane rates. This is the interleave bus option (IBO), which is discussed in Section 8.21. Note that the receive-elastic-store status bits are contained in RLS4 with the associated interrupt bits located in RIM4. These bits indicate a receive slip event, or when the e-store FIFO is in a full or empty condition. See the register definition for RLS4 for additional information. 78 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 RDATFMT 0 RESCR Receive Elastic Store Control Register 085h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 RGCLKEN 0 5 -- 0 4 RSZS 0 3 RESALGN 0 2 RESR 0 1 RESMDM 0 0 RESE 0 Note: RGPCKEN and RDATFMT are not associated with the elastic store and are explained in the fractional support section. Bit 0 / Receive-Elastic-Store Enable (RESE) 0 = elastic store is bypassed 1 = elastic store is enabled Bit 1 / Receive-Elastic Store Minimum Delay Mode (RESMDM) 0 = elastic stores operate at full two-frame depth 1 = elastic stores operate at 32-bit depth Bit 2 / Receive-Elastic Store Reset (RESR). Setting this bit from zero to 1 forces the read pointer into the same frame that the write pointer is exiting, minimizing the delay through the elastic store. If this command should place the pointers within the slip zone (see bit 4), then an immediate slip occurs and the pointers move back to opposite frames. Should be toggled after RSYSCLK has been applied and is stable. Do not leave this bit set HIGH. Bit 3 / Receive-Elastic Store Align (RESALGN). Setting this bit from zero to 1 forces the receive-elastic store's write/read pointers to a minimum separation of half a frame. No action will be taken if the pointer separation is already greater or equal to half a frame. If pointer separation is less than half a frame, the command will be executed and the data will be disrupted. Should be toggled after RSYSCLK has been applied and is stable. Must be cleared and set again for a subsequent align. Bit 4 / Receive Slip Zone Select (RSZS). This bit determines the minimum distance allowed between the elastic store read and write pointers before forcing a controlled slip. This bit is only applies during T1 to E1 or E1 to T1 conversion applications. 0 = force a slip at 9 bytes or less of separation (used for clustered blank channels) 1 = force a slip at 2 bytes or less of separation (used for distributed blank channels) Bit 5 / Unused. Must be set = 0 for proper operation. Bit 6 / Receive Gapped Clock Enable (RGCLKEN) 0 = RCHCLK functions normally 1 = Enable gapped bit clock output on RCHCLK Bit 7 / Receive-Channel Data Format (RDATFMT) 0 = 64kbps (data contained in all 8 bits) 1 = 56kbps (data contained in 7 out of the 8 bits) 79 DS26401 Octal T1/E1/J1 Framer 8.14.1 Mapping T1 Channels Onto a 2.048MHz Backplane Setting the RSCLKM bit in RIOCR.4 enables the receive-elastic store to operate with a 2.048MHz backplane (32 time slots/frame). In this mode, the user can choose which of the backplane channels on RSER receive the T1 data by programming the receive-blank channel-select registers (RBCS1-4). A logic 1 in the associated bit location forces RSER high for that backplane channel. Typically, the user wants to program 8 channels to be "blanked." The default (power-up) configuration blanks channels 25 to 32, so that the 24 T1 channels are mapped into the first 24 channels of the 2.048MHz backplane. If the user chooses to blank channel 1 (TS0) by setting RBCS1.0 = 1, then the F-bit is passed into the MSB of TS0 on RSER. For example, if: RBCS1 = 01h RBCS2 = 00h RBCS3 = 01h RBCS4 = FCh Then on RSER: Channel 1 (MSB) = F-bit Channel 1 (bits 1-7) = all ones Channels 2-16 = T1 channels 1-15 Channel 17 = all ones Channels 18-26 = T1 channels 16-24 Channels 27-32 = all ones Register Name: Register Description: Register Address: RBCS1, RBCS2, RBCS3, RBCS4 Receive Blank Channel Select Registers 0C0h, 0C1h, 0C2h, 0C3h [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8] Note that when two or more sequential channels are chosen to be blanked, the receive-slip zone-select bit (RSZS) should be set to zero. If the blank channels are distributed (such as 1, 5, 9, 13, 17, 21, 25, 29), then the RSZS bit can be set to 1, which may provide a lower occurrence of slips in certain applications. (MSB) CH8 CH16 CH24 CH32 (LSB) CH1 CH9 CH17 CH25 CH7 CH15 CH23 CH31 CH6 CH14 CH22 CH30 CH5 CH13 CH21 CH29 CH4 CH12 CH20 CH28 CH3 CH11 CH19 CH27 CH2 CH10 CH18 CH26 RBCS1 RBCS2 RBCS3 RBCS4 Bits 0-7 / Receive Blank Channel Select for Channels 1 to 32 (RBCS1-32). 0 = do not blank this channel (channel data is available on RSER) 1 = RSER is forced to all ones for this channel 80 DS26401 Octal T1/E1/J1 Framer 8.14.2 Additional Receive-Elastic-Store Information If the receive-side elastic store is enabled, then the user must provide either a 1.544MHz or 2.048MHz clock at the RSYSCLK pin. For higher rate system clock applications, see the Interleaved PCM Bus Option in Section 8.21. The user has the option of either providing a frame/multiframe sync at the RSYNC pin or having the RSYNC pin provide a pulse on frame/multiframe boundaries. If signaling reinsertion is enabled, the robbed-bit signaling data is realigned to the multiframe-sync input on RSYNC. Otherwise, a multiframe-sync input on RSYNC is treated as a simple frame boundary by the elastic store. The framer always indicated frame boundaries on the network side of the elastic store through the RFSYNC output, whether the elastic store is enabled or not. Multiframe boundaries are always indicated through the RMSYNC output. If the elastic store is enabled, RMSYNC outputs the multiframe boundary on the backplane side of the elastic store. When the device is receiving T1, and the backplane is enabled for 2.048MHz operation, the RMSYNC signal outputs the T1 multiframe boundaries as delayed through the elastic store. If the user selects to apply a 2.048MHz clock to the RSYSCLK pin, then the backplane blank-channel-select registers (RBCS1-4) can be used to determine which channels have the data output at RSER forced to all ones. If the user chooses to blank time slot 0, then the F-bit is passed into the MSB of TS0. If the two-frame elastic buffer either fills or empties, a controlled slip occurs. If the buffer empties, a full frame of data is repeated at RSER, and the RLS4.5 and RLS4.6 bits are set to 1. If the buffer fills, a full frame of data is deleted, and the RLS4.5 and RLS4.7 bits are set to 1. 8.14.2.1 Elastic Store Initialization There are two elastic-store initializations that can be used to improve performance in certain applications--the elastic-store reset and elastic-store align. Both of these involve the manipulation of the elastic store's read and write pointers, and are useful primarily in synchronous applications (RSYSCLK/TSYSCLK are locked to RCLK/TCLK respectively). The elastic-store reset is used to minimize the delay through the elastic store. The elastic-store align bit is used to center the read/write pointers to the extent possible. Elastic Store Delay After Initialization INITIALIZATION Receive-Elastic-Store Reset Transmit-Elastic-Store Reset Receive-Elastic-Store Align Transmit-Elastic-Store Align N = 9 for RSZS = 0 N = 2 for RSZS = 1 REGISTER BIT RESCR.2 TESCR.2 RESCR.3 TESCR.3 DELAY N bytes < Delay < 1 Frame + N bytes N bytes < Delay < 1 Frame + N bytes 1/2 Frame < Delay < 1 1/2 Frames 1/2 Frame < Delay < 1 1/2 Frames 8.14.2.2 Minimum-Delay Mode Elastic-store minimum-delay mode can be used when the elastic store's system clock is locked to its network clock (i.e., RCLK locked to RSYSCLK for the receive side and TCLK locked to TSYSCLK for the transmit side). RESCR.1 enables the receive-elastic-store minimum-delay mode. When enabled, the elastic stores are forced to a maximum depth of 32 bits instead of the normal two-frame depth. This feature is useful primarily in applications that interface to a 2.048MHz bus. Certain restrictions apply when minimum-delay mode is used. In addition to the restriction mentioned above, RSYNC must be configured as an output when the receive-elastic store is in minimum-delay mode and TSYNC must be configured as an output when transmit-minimum-delay mode is enabled. In a typical application, RSYSCLK and TSYSCLK are locked to RCLK, and RSYNC (frame-output mode) is connected to TSSYNC (frame-input mode). All the slip contention logic in the framer is disabled (since slips cannot occur). On power-up, after the RSYSCLK and TSYSCLK signals have locked to their respective network clock signals, the elastic-store-reset bit (RESCR.2) should be toggled from zero to 1 to ensure proper operation. 81 DS26401 Octal T1/E1/J1 Framer 8.15 Fractional T1 Support (Gapped-Clock Mode) The DS26401 can be programmed to output gapped clocks for selected channels in the receive and transmit paths to simplify connections into a USART or LAPD controller in Fractional T1/E1 or ISDN-PRI applications. When the gapped-clock feature is enabled, a gated clock is output on the RCHCLK signal. The channel selection is controlled through the receive-gapped-clock channel-select registers (RGCCS1-RGCCS4). The receive path is enabled for gapped-clock mode with the RGCLKEN bit (RESCR.6). Both 56kbps and 64kbps channel formats are supported as determined by RESCR.7. When 56kbps mode is selected, the clock corresponding to the data/control bit in the channel is omitted (only the seven most significant bits of the channel have clocks). Register Name: Register Description: Register Address: RGCCS1, RGCCS2, RGCCS3, RGCCS4 Receive-Gapped-Clock Channel-Select Registers 0CCh, 0CDh, 0CEh, 0CFh [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8] (LSB) (MSB) CH8 CH16 CH24 CH32 CH7 CH15 CH23 CH31 CH6 CH14 CH22 CH30 CH5 CH13 CH21 CH29 CH4 CH12 CH20 CH28 CH3 CH11 CH19 CH27 CH2 CH10 CH18 CH26 CH1 CH9 CH17 CH25/F-Bit RGCCS 1 RGCCS 2 RGCCS 3 RGCCS 4* Bits 0 to 7 / Receive Channels 1 to 32 Gapped-Clock Channel Select Bits (CH1 to CH32) 0 = no clock is present on RCHCLK during this channel time 1 = force a clock on RCHCLK during this channel time. The clock will be synchronous with RCLK if the elastic store is disabled, and synchronous with RSYSCLK if the elastic store is enabled. *Note that RGCCS4 has two functions: When 2.048MHz backplane mode is selected, this register allows the user to enable the gapped clock on RCHCLK for any of the 32 possible backplane channels. When 1.544MHz backplane mode is selected, the LSB of this register determines whether or not a clock is generated on RCHCLK during the F-bit time: RGCCS4.0 = 0: do not generate a clock during the F-bit RGCCS4.0 = 1: generate a clock during the F-bit In this mode, RGCCS4.1--RGCCS4.7 should be set to 0. 82 DS26401 Octal T1/E1/J1 Framer 8.16 T1 Bit-Oriented Code (BOC) Controller The DS26401 contains a BOC generator on the transmit side and a BOC detector on the receive side. The BOC function is available only in T1 mode. In ESF mode, the DS26401 continuously monitors the receive message bits for a valid BOC message. The BOCdetect (BD) status bit at RLS7.0 is set once a valid message has been detected for time determined by the receiveBOC-filter bits RBF0 and RBF1 in the RBOCC register. The 6-bit BOC message is available in the RBOC register. Once the user has cleared the BD bit, it remains clear until a new BOC is detected (or the same BOC is detected following a BOC-clear event). The BOC-clear (BC) bit at RLS7.1 is set when a valid BOC is no longer being detected for a time determined by the receive-BOC-disintegration bits RBD0 and RBD1 in the RBOCC register. The BD and BC status bits can create a hardware interrupt on the INT signal as enabled by the associated interrupt mask bits in the RIM7 register. Register Name: Register Description: Register Address: Bit # Name Default 7 RBR 0 RBOCC Receive BOC Control Register 015h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 RBD1 0 4 RBD0 0 3 -- 0 2 RBF1 0 1 RBF0 0 0 -- 0 Bits 0, 3, 6 / Unused. Must be set = 0 for proper operation. Bits 1 to 2 / Receive-BOC-Filter Bits (RBF0, RBF1). The BOC filter sets the number of consecutive patterns that must be received without error prior to an indication of a valid message. RBF1 0 0 1 1 RBF0 0 1 0 1 Consecutive BOC Codes for Valid Sequence Identification None 3 5 7 (Note 1) Bits 4 to 5 / Receive-BOC-Disintegration Bits (RBD0, RBD1). The BOC Disintegration filter sets the number of message bits that must be received without a valid BOC in order to set the BC bit indicating that a valid BOC is no longer being received. RBD1 0 0 1 1 RBD0 0 1 0 1 Consecutive Message Bits for BOC Clear Identification 16 32 48 64 (Note 1) Bit 7 / Receive-BOC Reset (RBR). A 0-to-1 transition resets the BOC circuitry. Must be cleared and set again for a subsequent reset. Modifications to the RBF0, RBF1, RBD0, and RBD1 bits are not applied to the BOC controller until a BOC reset has been completed. Note 1: The DS26401's BOC controller does not integrate and disintegrate concurrently. Therefore, if the maximum integration time and the maximum disintegration time are used together, BOC messages that repeat fewer than 11 times may not be detected. 83 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 RBOC Receive BOC Register 63h + (200h * n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 RBOC5 0 4 RBOC4 0 3 RBOC3 0 2 RBOC2 0 1 RBOC1 0 0 RBOC0 0 The RBOC Register always contains the last valid BOC received. Bit 0 / BOC Bit 0 (RBOC0) Bit 1 / BOC Bit 1 (RBOC1) Bit 2 / BOC Bit 2 (RBOC2) Bit 3 / BOC Bit 3 (RBOC3) Bit 4 / BOC Bit 4 (RBOC4) Bit 5 / BOC Bit 5 (RBOC5) Bits 6, 7 / Unused 84 DS26401 Octal T1/E1/J1 Framer 8.17 Receive SLC-96 Operation In an SLC-96-based transmission scheme, the standard Fs-bit pattern is robbed to make room for a set of message fields. The SLC-96 multiframe is made up of six D4 superframes, hence it is 72 frames long. In the 72-frame SLC96 multiframe, 36 of the framing bits are the normal Ft pattern and the other 36 bits are divided into alarm, maintenance, spoiler, and concentrator bits, as well as 12 bits of the normal Fs pattern. Additional SLC-96 information can be found in BellCore document TR-TSY-000008. To enable the DS26401 to synchronize onto an SLC-96 pattern, the following configuration should be used: Set to D4 framing mode (RCR1.5 = 1) Set to cross-couple Ft and Fs bits (RCR1.3 = 1) Enable SLC-96 synchronizer (RCR2.4 = 1) Set to minimum sync time (RCR1.7 = 0) The status bit RSLC96 located at RLS7.3 is useful for retrieving SLC-96 message data. The RSLC96 bit indicates when the framer has received the 12-bit Fs-alignment pattern and updated the data-link registers RSLC1-RSLC3 with the latest message data from the incoming data stream. Once the RSLC96 bit is set, the user has 2ms to retrieve the most recent message data from the RSLC1/2/3 registers. Note that RSLC96 is not set if the DS26401 is unable to detect the 12-bit SLC-96 alignment pattern. Register Name: Register Description: Register Address: RSLC1, RSLC2, RSLC3 Receive SLC96 Data Link Registers 064h, 065h, 066h [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8] (LSB) C1 C9 M3 (MSB) C8 M2 S=1 C7 M1 S4 C6 S=0 S3 C5 S=1 S2 C4 S=0 S1 C3 C11 A2 C2 C10 A1 RSLC1 RSLC2 RSLC3 85 DS26401 Octal T1/E1/J1 Framer 8.18 Receive FDL In the receive section, the recovered FDL bits or Fs bits are shifted bit-by-bit into the receive FDL register (RFDL). Since the RFDL is 8 bits in length, it fills up every 2ms (8 x 250ms). The framer signals an external microcontroller that the buffer has filled through the RLS7.2 bit. If enabled through RIM7.2, the INT pin toggles low, indicating that the buffer has filled and needs to be read. The user has 2ms to read this data before it is lost. Note that no zero destuffing is applied for the data provided through the RFDL register. Register Name: Register Description: Register Address: Bit # Name Default 7 RFDL7 0 RFDL Receive FDL Register 062h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 RFDL6 0 5 RFDL5 0 4 RFDL4 0 3 RFDL3 0 2 RFDL2 0 1 RFDL1 0 0 RFDL0 0 The receive FDL register (RFDL) reports the incoming facility data link (FDL) or the incoming Fs bits. The LSB is received first. In D4 framing mode, RFDL updates on multiframe boundaries and reports the six Fs bits in RFDL0- RFDL5. Bit 0 / Receive FDL Bit 0 (RFDL0). LSB of the received FDL code. Bit 1 / Receive FDL Bit 1 (RFDL1) Bit 2 / Receive FDL Bit 2 (RFDL2) Bit 3 / Receive FDL Bit 3 (RFDL3) Bit 4 / Receive FDL Bit 4 (RFDL4) Bit 5 / Receive FDL Bit 5 (RFDL5) Bit 6 / Receive FDL Bit 6 (RFDL6) Bit 7 / Receive FDL Bit 7 (RFDL7). MSB of the received FDL code. 86 DS26401 Octal T1/E1/J1 Framer 8.19 Programmable In-Band Loop-Code Detection The DS26401 can generate and detect a repeating bit pattern from 1 to 8 bits or 16 bits in length. This function is available only in T1 mode. The framer has three programmable pattern detectors. Typically, two of the detectors are used for loop-up and loop-down code detection. The user programs the codes to be detected in the receive-upcode definition (RUPCD1 and RUPCD2) registers and the receive-down-code definition (RDNCD1 and RDNCD2) registers, and the length of each pattern is selected through the RIBCC register. A third detector (spare) is defined and controlled through the RSPCD1/RSPCD2 and RSCC registers. When detecting a 16-bit pattern, both receivecode-definition registers are used together to form a 16-bit register. For 8-bit patterns, both receive-code-definition registers are filled with the same value. Detection of a 1-, 2-, 3-, 4-, 5-, 6-, and 7-bit pattern only requires the first receive-code-definition register to be filled. The framer detects repeating pattern codes in framed and unframed circumstances with bit-error rates as high as 10E-2. The detectors can handle F-bit-inserted and F-bit-overwrite patterns. Writing the least significant byte of the receive-code-definition register resets the integration period for that detector. The code detector has a nominal integration period of 36ms. Therefore, after about 36ms of receiving a valid code, the proper status bit (LUP, LDN, and LSP) is set to 1. Note that real-time status bits, as well as latched set and clear bits, are available for LUP, LDN, and LSP (RRTS3 and RLS3). Normally codes are sent for 5 seconds. It is recommended that the software poll the framer every 50ms to 1000ms until 5 seconds has elapsed to ensure the code is continuously present. Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 RIBCC Receive In-Band Code Control Register 082h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 RUP2 0 4 RUP1 0 3 RUP0 0 2 RDN2 0 1 RDN1 0 0 RDN0 0 Bits 0 to 2 / Receive-Down-Code Length Definition Bits (RDN0 to RDN2) RDN2 0 0 0 0 1 1 1 1 RDN1 0 0 1 1 0 0 1 1 RDN0 0 1 0 1 0 1 0 1 Length Selected (bits) 1 2 3 4 5 6 7 8 / 16 Bits 3 to 5 / Receive-Up-Code Length Definition Bits (RUP0 to RUP2) RUP2 0 0 0 0 1 1 1 1 RUP1 0 0 1 1 0 0 1 1 RUP0 0 1 0 1 0 1 0 1 Length Selected (bits) 1 2 3 4 5 6 7 8 / 16 87 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 C7 0 RUPCD1 Receive-Up Code-Definition Register 1 0ACh + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Note: Writing this register resets the detector's integration period. Bit 0 / Receive-Up Code-Definition Bit 0 (C0). A don't care if a 1- to 7-bit length is selected. Bit 1 / Receive-Up Code-Definition Bit 1 (C1). A don't care if a 1- to 6-bit length is selected. Bit 2 / Receive-Up Code-Definition Bit 2 (C2). A don't care if a 1- to 5-bit length is selected. Bit 3 / Receive-Up Code-Definition Bit 3 (C3). A don't care if a 1- to 4-bit length is selected. Bit 4 / Receive-Up Code-Definition Bit 4 (C4). A don't care if a 1- to 3-bit length is selected. Bit 5 / Receive-Up Code-Definition Bit 5 (C5). A don't care if a 1- or 2-bit length is selected. Bit 6 / Receive-Up Code-Definition Bit 6 (C6). A don't care if a 1-bit length is selected. Bit 7 / Receive-Up Code-Definition Bit 7 (C7). First bit of the repeating pattern. Register Name: Register Description: Register Address: Bit # Name Default 7 C7 0 RUPCD2 Receive-Up Code-Definition Register 2 0ADh + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Bit 0 / Receive-Up Code-Definition Bit 0 (C0). A don't care if a 1- to 7-bit length is selected. Bit 1 / Receive-Up Code-Definition Bit 1 (C1). A don't care if a 1- to 7-bit length is selected. Bit 2 / Receive-Up Code-Definition Bit 2 (C2). A don't care if a 1- to 7-bit length is selected. Bit 3 / Receive-Up Code-Definition Bit 3 (C3). A don't care if a 1- to 7-bit length is selected. Bit 4 / Receive-Up Code-Definition Bit 4 (C4). A don't care if a 1- to 7-bit length is selected. Bit 5 / Receive-Up Code-Definition Bit 5 (C5). A don't care if a 1- to 7-bit length is selected. Bit 6 / Receive-Up Code-Definition Bit 6 (C6). A don't care if a 1- to 7-bit length is selected. Bit 7 / Receive-Up Code-Definition Bit 7 (C7). A don't care if a 1- to 7-bit length is selected. 88 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 C7 0 RDNCD1 Receive-Down Code-Definition Register 1 0AEh + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Note: Writing this register resets the detector's integration period. Bit 0 / Receive-Down Code-Definition Bit 0 (C0). A don't care if a 1- to 7-bit length is selected. Bit 1 / Receive-Down Code-Definition Bit 1 (C1). A don't care if a 1- to 6-bit length is selected. Bit 2 / Receive-Down Code-Definition Bit 2 (C2). A don't care if a 1- to 5-bit length is selected. Bit 3 / Receive-Down Code-Definition Bit 3 (C3). A don't care if a 1- to 4-bit length is selected. Bit 4 / Receive-Down Code-Definition Bit 4 (C4). A don't care if a 1- to 3-bit length is selected. Bit 5 / Receive-Down Code-Definition Bit 5 (C5). A don't care if a 1- or 2-bit length is selected. Bit 6 / Receive-Down Code-Definition Bit 6 (C6). A don't care if a 1-bit length is selected. Bit 7 / Receive-Down Code-Definition Bit 7 (C7). First bit of the repeating pattern. Register Name: Register Description: Register Address: Bit # Name Default 7 C7 0 RDNCD2 Receive-Down Code-Definition Register 2 0AFh + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Bit 0 / Receive-Down Code Definition Bit 0 (C0). A don't care if a 1- to 7-bit length is selected. Bit 1 / Receive-Down Code-Definition Bit 1 (C1). A don't care if a 1- to 7-bit length is selected. Bit 2 / Receive-Down Code-Definition Bit 2 (C2). A don't care if a 1- to 7-bit length is selected. Bit 3 / Receive-Down Code-Definition Bit 3 (C3). A don't care if a 1- to 7-bit length is selected. Bit 4 / Receive-Down Code-Definition Bit 4 (C4). A don't care if a 1- to 7-bit length is selected. Bit 5 / Receive-Down Code-Definition Bit 5 (C5). A don't care if a 1- to 7-bit length is selected. Bit 6 / Receive-Down Code-Definition Bit 6 (C6). A don't care if a 1- to 7-bit length is selected. Bit 7 / Receive-Down Code-Definition Bit 7 (C7). A don't care if a 1- to 7-bit length is selected. 89 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 RSCC In-Band Receive-Spare Control Register 089h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 RSC2 0 1 RSC1 0 0 RSC0 0 Bits 0 to 2 / Receive-Spare Code-Length Definition Bits (RSC0 to RSC2) RSC2 0 0 0 0 1 1 1 1 RSC1 0 0 1 1 0 0 1 1 RSC0 0 1 0 1 0 1 0 1 Length Selected (bits) 1 2 3 4 5 6 7 8 / 16 Bits 3-7 / Unused. Must be set = 0 for proper operation. 90 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 C7 0 RSCD1 Receive-Spare Code-Definition Register 1 09Ch + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Note: Writing this register resets the detector's integration period. Bit 0 / Receive-Spare Code-Definition Bit 0 (C0). A don't care if a 1- to 7-bit length is selected. Bit 1 / Receive-Spare Code-Definition Bit 1 (C1). A don't care if a 1- to 6-bit length is selected. Bit 2 / Receive-Spare Code-Definition Bit 2 (C2). A don't care if a 1- to 5-bit length is selected. Bit 3 / Receive-Spare Code-Definition Bit 3 (C3). A don't care if a 1- to 4-bit length is selected. Bit 4 / Receive-Spare Code-Definition Bit 4 (C4). A don't care if a 1- to 3-bit length is selected. Bit 5 / Receive-Spare Code-Definition Bit 5 (C5). A don't care if a 1- or 2-bit length is selected. Bit 6 / Receive-Spare Code-Definition Bit 6 (C6). A don't care if a 1-bit length is selected. Bit 7 / Receive-Spare Code-Definition Bit 7 (C7). First bit of the repeating pattern. Register Name: Register Description: Register Address: Bit # Name Default 7 C7 0 RSCD2 Receive-Spare Code-Definition Register 2 09Dh + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Bit 0 / Receive-Spare Code-Definition Bit 0 (C0). A don't care if a 1- to 7-bit length is selected. Bit 1 / Receive-Spare Code-Definition Bit 1 (C1). A don't care if a 1- to 7-bit length is selected. Bit 2 / Receive-Spare Code-Definition Bit 2 (C2). A don't care if a 1- to 7-bit length is selected. Bit 3 / Receive-Spare Code-Definition Bit 3 (C3). A don't care if a 1- to 7-bit length is selected. Bit 4 / Receive-Spare Code-Definition Bit 4 (C4). A don't care if a 1- to 7-bit length is selected. Bit 5 / Receive-Spare Code-Definition Bit 5 (C5). A don't care if a 1- to 7-bit length is selected. Bit 6 / Receive-Spare Code-Definition Bit 6 (C6). A don't care if a 1- to 7-bit length is selected. Bit 7 / Receive-Spare Code-Definition Bit 7 (C7). A don't care if a 1- to 7-bit length is selected. 91 DS26401 Octal T1/E1/J1 Framer 8.20 Receive HDLC Controller The HDLC controller can be mapped into a single time slot, or Sa4 to Sa8 bits (E1 mode), or the FDL (T1 mode). The HDLC controller has a 64-byte FIFO buffer in the transmit and receive paths. The user can select any specific bits within the time slot(s) to assign to the HDLC controller, as well as specific Sa bits (E1 mode). The HDLC controller performs the necessary overhead for generating and receiving performance report messages (PRM) as described in ANSI T1.403 and the messages as described in AT&T TR54016. The HDLC controller automatically generates and detects flags; generates and checks the CRC checksum; generates and detects abort sequences and stuffs and destuffs zeros; and byte aligns to the data stream. The 64-byte buffers in the HDLC controller are large enough to allow a full PRM to be received or transmitted without host intervention. Register Name: Register Description: Register Address: Bit # Name Default 7 RCRCD 0 RHC Receive HDLC Control Register 010h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 RHR 0 5 RHMS 0 4 RHCS4 0 3 RHCS3 0 2 RHCS2 0 1 RHCS1 0 0 RHCS0 0 Bit 0 to Bit 4 / Receive HDLC Channel Select (RHCSx). These bits determine which DS0 is mapped to the HDLC controller when enabled with RHMS = 0. RHCS0 to RHCS4 = all zeros selects channel 1, RHCS0 to RHCS4 = all ones selects channel 32 (E1) Bit 5 / Receive HDLC Mapping Select (RHMS) 0 = Receive HDLC assigned to channels 1 = Receive HDLC assigned to FDL (T1 mode), Sa bits (E1 mode) Bit 6 / Receive HDLC Reset (RHR). Resets the receive-HDLC controller and flushes the receive FIFO. Must be cleared and set again for a subsequent reset. 0 = Normal operation 1 = Reset receive HDLC controller and flush the receive FIFO Bit 7 / Receive CRC16 Display (RCRCD) 0 = Do not write received CRC16 code to FIFO 1= Write received CRC16 code to FIFO after last octet of packet 92 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 BSE8 0 RHBSE Receive HDLC Bit Suppress Register 011h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 BSE7 0 5 BSE6 0 4 BSE5 0 3 BSE4 0 2 BSE3 0 1 BSE2 0 0 BSE1 0 Bit 0 / Receive Channel Bit 1 Suppress (BSE1). LSB of the channel. Set to one to stop this bit from being used. Bit 1 / Receive Channel Bit 2 Suppress (BSE2). Set to one to stop this bit from being used Bit 2 / Receive Channel Bit 3 Suppress (BSE3). Set to one to stop this bit from being used Bit 3 / Receive Channel Bit 4 Suppress (BSE4). Set to one to stop this bit from being used Bit 4 / Receive Channel Bit 5 Suppress (BSE5). Set to one to stop this bit from being used Bit 5 / Receive Channel Bit 6 Suppress (BSE6). Set to one to stop this bit from being used. Bit 6 / Receive Channel Bit 7 Suppress (BSE7). Set to one to stop this bit from being used. Bit 7 / Receive Channel Bit 8 Suppress (BSE8). MSB of the channel. Set to one to stop this bit from being used. 93 DS26401 Octal T1/E1/J1 Framer 8.20.1 HDLC FIFO Control Control of the receive FIFO is accomplished through the receive-HDLC FIFO control (RHFC). The FIFO control register sets the watermarks for the receive FIFO. When the receive FIFO fills above the high watermark, the RHWM bit (RRTS5.1) is set. RHWM is a real-time bit and remains set as long as the receive FIFO's write pointer is above the watermark. If enabled, this condition can also cause an interrupt through the INT pin. Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 RHFC Receive HDLC FIFO Control Register 087h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 -- 0 1 RFHWM1 0 0 RFHWM0 0 Bits 0 to 1 / Receive FIFO High Watermark Select (RFHWM0 to RFHWM1) RFHWM1 0 0 1 1 RFHWM0 0 1 0 1 Receive FIFO Watermark (bytes) 4 16 32 48 Bits 2-7 / Unused. Must be set = 0 for proper operation. 94 DS26401 Octal T1/E1/J1 Framer 8.20.2 Receive-Packet-Bytes Available The lower 6 bits of the receive-packet-bytes-available register indicates the number of bytes (0 through 64) that can be read from the receive FIFO. The value indicated by this register informs the host as to how many bytes can be read from the receive FIFO without going past the end of a message. This value refers to one of four possibilities: the first part of a packet, the continuation of a packet, the last part of a packet, or a complete packet. After reading the number of bytes indicated by this register, the host then checks the HDLC status registers for detailed message status. If the value in the RHPBA register refers to the beginning portion of a message or continuation of a message, then the MSB of the RHPBA register returns a 1. This indicates that the host may safely read the number of bytes returned by the lower 6 bits of the RHPBA register, but there is no need to check the information register since the packet has not yet terminated (successfully or otherwise). Register Name: Register Description: Register Address: RHPBA Receive HDLC Packet Bytes Available Register 0B5h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 Bit # Name Default 7 MS 0 6 RPBA6 0 5 RPBA5 0 4 RPBA4 0 3 RPBA3 0 2 RPBA2 0 1 RPBA1 0 0 RPBA0 0 Bits 0-6 / Receive FIFO Packet Bytes Available Count (RPBA0 to RPBA6). RPBA0 is the LSB. Bit 7 / Message Status (MS) 0 = Bytes indicated by RPBA0 through RPBA6 are the end of a message. Host must check the HDLC Status register for details. 1 = Bytes indicated by RPBA0 through RPBA6 are the beginning or continuation of a message. The host does not need to check the HDLC status. Register Name: Register Description: Register Address: Bit # Name Default 7 RHD7 0 RHF Receive HDLC FIFO Register 0B6h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 RHD6 0 5 RHD5 0 4 RHD4 0 3 RHD3 0 2 RHD2 0 1 RHD1 0 0 RHD0 0 Bit 0 / Receive HDLC Data Bit 0 (RHD0). LSB of a HDLC packet data byte. Bit 1 / Receive HDLC Data Bit 1 (RHD1) Bit 2 / Receive HDLC Data Bit 2 (RHD2) Bit 3 / Receive HDLC Data Bit 3 (RHD3) Bit 4 / Receive HDLC Data Bit 4 (RHD4) Bit 5 / Receive HDLC Data Bit 5 (RHD5) Bit 6 / Receive HDLC Data Bit 6 (RHD6) Bit 7 / Receive HDLC Data Bit 7 (RHD7). MSB of a HDLC packet data byte. 95 DS26401 Octal T1/E1/J1 Framer 8.20.3 HDLC Status and Information RRTS5 and RLS5 provide status information for the receive HDLC controller. When a particular event has occurred (or is occurring), the appropriate bit in one of these registers is set to 1. With the latched bits, when an event occurs and a bit is set to 1, it remains set until the user reads that bit. The bit is cleared when it is read and it is not set again until the event has occurred again. The real-time bits report the current instantaneous conditions that are occurring and the history of these bits is not latched. Like the other latched-status registers, the user follows a read of the status bit with a write. The byte written to the register informs the device which of the latched bits the user wishes to clear (the real-time bits are not affected by writing to the status register). The user writes a byte to one of these registers, with a 1 in the bit positions the user wishes to clear and a zero in the bit positions the user wishes not to clear. The HDLC status register RLS5 can initiate a hardware interrupt through the INT output signal. Each of the events in this register can be either masked or unmasked from the interrupt pin through the receive-HDLC interrupt-mask register (RIM5). Interrupts force the INT signal low when the event occurs. The INT pin is allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the interrupt to occur. Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 RRTS5 Receive Real-Time Status Register 5 (HDLC) 0B4h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 PS2 0 5 PS1 0 4 PS0 0 3 -- 0 2 -- 0 1 RHWM 0 0 RNE 0 Note: All bits in this register are real-time. Bit 0 / Receive-FIFO Not Empty Condition (RNE). Set when the receive 64-byte FIFO has at least one byte available for a read. This is a real-time bit. Bit 1 / Receive-FIFO Above High-Watermark Condition (RHWM). Set when the receive 64-byte FIFO fills beyond the high watermark as defined by the receive-HDLC FIFO control register (RHFC).This is a real-time bit. Bits 2, 3, 7 / Unused Bits 4 to 6 / Receive Packet Status (PS0 to PS2). These are real-time bits indicating the status as of the last read of the receive FIFO. PS2 0 0 0 0 1 PS1 0 0 1 1 0 PS0 0 1 0 1 0 PACKET STATUS In Progress: End of message has not yet been reached. Packet OK: Packet ended with correct CRC codeword. CRC Error: A closing flag was detected, preceded by a corrupt CRC codeword. Abort: Packet ended because an abort signal was detected (seven or more ones in a row). Overrun: HDLC controller terminated reception of packet because receive FIFO is full. 96 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 RLS5 Receive Latched Status Register 5 (HDLC) 094h + (200h x n) : where n = 0 to 7, or Ports 1 to 8 6 -- 0 5 ROVR 0 4 RHOBT 0 3 RPE 0 2 RPS 0 1 RHWMS 0 0 RNES 0 Note: All bits in this register are latched and can cause interrupts. Bit 0 / Receive-FIFO Not Empty Set Event (RNES). Set when the receive FIFO has transitioned from `empty' to `not-empty' (at least one byte has been put into the FIFO). Rising edge detect of RNE. Bit 1 / Receive-FIFO Above High-Watermark Set Event (RHWMS). Set when the receive-64-byte FIFO crosses the high watermark as defined by the receive HDLC FIFO control register (RHFC). Rising edge detect of RHWM. Bit 2 / Receive Packet Start Event (RPS). Set when the HDLC controller detects an opening byte. This is a latched bit and will be cleared when read. Bit 3 / Receive Packet End Event (RPE). Set when the HDLC controller detects either the finish of a valid message (i.e., CRC check complete) or when the controller has experienced a message fault such as a CRC checking error, or an overrun condition, or an abort has been seen. This is a latched bit and is cleared when read. Bit 4 / Receive HDLC Opening Byte Event (RHOBT). Set when the next byte available in the receive FIFO is the first byte of a message. Bit 5 / Receive FIFO Overrun (ROVR). Set when the receive HDLC controller has terminated packet reception because the FIFO buffer is full. Bits 6, 7 / Unused 97 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 RIM5 Receive Interrupt Mask 5 (HDLC) 0A4h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 ROVR 0 4 RHOBT 0 3 RPE 0 2 RPS 0 1 RHWMS 0 0 RNES 0 Bit 0 / Receive-FIFO Not Empty Set Event (RNES) 0 = interrupt masked 1 = interrupt enabled Bit 1 / Receive-FIFO Above High-Watermark Set Event (RHWMS) 0 = interrupt masked 1 = interrupt enabled Bit 2 / Receive-Packet-Start Event (RPS) 0 = interrupt masked 1 = interrupt enabled Bit 3 / Receive-Packet-End Event (RPE) 0 = interrupt masked 1 = interrupt enabled Bit 4 / Receive-HDLC Opening-Byte Event (RHOBT) 0 = interrupt masked 1 = interrupt enabled Bit 5 / Receive-FIFO Overrun (ROVR) 0 = interrupt masked 1 = interrupt enabled Bits 6, 7 / Unused. Must be set = 0 for proper operation. 98 DS26401 Octal T1/E1/J1 Framer 8.20.4 HDLC Receive Example The HDLC status registers in the DS26401 allow for flexible software interface to meet the user's preferences. When receiving HDLC messages, the host can choose to be interrupt-driven, or to poll to desired status registers, or a combination of polling and interrupt processes can be used. Figure 8-3 shows an example routine for using the DS26401 HDLC receiver. Figure 8-3. Receive HDLC Example Configure Receive HDLC Controller (RHC, RHBSE, RHFC) Reset Receive HDLC Controller (RHC.6) Start New Message Buffer Enable Interrupts RPE and RHWM Interrupt? NO No Action Required Work Another Process YES Read Register RHPBA Read N Bytes From Rx HDLC FIFO (RHF) N = RHPBA[5..0] NO MS = 0? (MS = RHPBA[7]) YES Read RRTS5 for Packet Status (PS2..0) Take appropriate action 99 DS26401 Octal T1/E1/J1 Framer 8.21 Interleaved PCM Bus Operation (IBO) In many architectures, the PCM outputs of individual framers are combined into higher-speed PCM buses to simplify transport across the system backplane. The DS26401 can be configured to allow PCM data to be multiplexed into higher-speed buses, eliminating external hardware, and saving board space and cost. The DS26401 can be configured for channel or frame interleave. The interleaved PCM bus option (IBO) supports three bus speeds. The 4.096MHz bus speed allows two PCM data streams to share a common bus. The 8.192MHz bus speed allows four PCM data streams to share a common bus. The 16.384MHz bus speed allows eight PCM data streams to share a common bus. The receive-elastic stores of each transceiver must be enabled. Through the IBO register, the user can configure each framer for a specific bus position. For all IBO bus configurations, each framer is assigned an exclusive position in the high-speed PCM bus. The 8kHz frame sync can be generated from the system backplane or from the first device on the bus. All other devices on the bus must have their frame syncs configured as inputs. Relative to this common frame sync, the devices await their turn to drive or sample the bus according to the settings of the DA0, DA1, and DA2 bits of the RIBOC register. 8.21.1 Channel Interleave In channel-interleave mode, data is output to the PCM data-out bus one channel at a time from each of the connected DS26401s until all channels of frame n from each framer has been placed on the bus. This mode can be used even when the DS26401s are operating asynchronous to each other. The elastic stores manage slip conditions. The DS26401 provides an active-low signal (RIBO_OEB) during bus active times. RIBO_OEB can be used to control a bus multiplexer or tri-state buffer control. Functional timing is given in Figure 13-6. 8.21.2 Frame Interleave In frame-interleave mode, data is output to the PCM data bus one frame at a time from each of the framers. This mode is used only when all connected DS26401s are operating in a synchronous fashion (all inbound T1 or E1 lines are synchronous) and are synchronous with the system clock (system clock derived from T1 or E1 line). In this mode, slip conditions are not allowed. Functional timing is given in Figure 13-7. 100 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 RIBOC Receive Interleave Bus Operation Control Register 088h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 IBS1 0 5 IBS0 0 4 IBOSEL 0 3 IBOEN 0 2 DA2 0 1 DA1 0 0 DA0 0 Bits 0 to 2 / Device Assignment Bits (DA0 to DA2) DA2 0 0 0 0 1 1 1 1 DA1 0 0 1 1 0 0 1 1 DA0 0 1 0 1 0 1 0 1 Device Position 1st device on bus 2nd device on bus 3rd device on bus 4th device on bus 5th device on bus 6th device on bus 7th device on bus 8th device on bus Bit 3 / Interleave Bus Operation Enable (IBOEN) 0 = Interleave Bus Operation disabled. 1 = Interleave Bus Operation enabled. Bit 4 / Interleave Bus Operation Select (IBOSEL). This bit selects channel or frame interleave mode. 0 = Channel Interleave 1 = Frame Interleave Bits 5 to 6 / IBO Bus Size bit 1 (IBS0 to IBS1). Indicates how many devices on the bus. IBS1 0 0 1 1 IBS0 0 1 0 1 Bus Size 2 Devices on bus (4.096MHz) 4 Devices on bus (8.192MHz) 8 Devices on bus (16.384MHz) Reserved for future use Bit 7 / Unused. Must be set = 0 for proper operation. 101 DS26401 Octal T1/E1/J1 Framer 8.22 Interfacing the T1 Rx Framer to the BERT Data from the DS26401 receive framer can be ported to the on-chip BERT by using the registers described below. Either framed or unframed data can be provided to the BERT, controlled by the RBFUS bit in the RBICR. Any single DS0 or combination of DS0s can be extracted from the data stream up to the entire T1 payload, as controlled by the RBCS registers. Note that one BERT resource is shared among all 8 framers. Therefore, the RBEN bit should be set for only one framer at a time. If multiple framers have the RBEN bit set, the lower number framer is assigned the resource. Details concerning the on-chip BERT can be found in Section 12. Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 RBICR Receive BERT Interface Control Register 08Ah + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 RBDC 0 1 RBFUS 0 0 RBEN 0 Bit 0 / Receive BERT Enable (RBEN) 0 = Receive BERT is not assigned to this framer. 1 = Receive BERT is assigned to this framer. Bit 1 / Receive BERT Framed/Unframed Select (RBFUS) 0 = The framer does not provide data from the F-bit position (framed). 1 = The framer clocks data from the F-bit position (unframed). Bit 2 / Receive BERT Direction Control (RBDC) 0 = Receive Path: The BERT receives data from the network side via RPOS and RNEG. 1 = Backplane: The BERT receives data from the system backplane via the TSER pin. Bits 3-7 / Unused. Must be set = 0 for proper operation. 102 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: RBCS1, RBCS2, RBCS3 Receive BERT Channel Select Registers 0D4h, 0D5h, 0D6h [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8] Setting any of the CH1 through CH24 bits in the RBCS1 through RBCS3 registers maps data from those channels to the on-board BERT. RBEN must be set to 1 for these registers to function. Multiple or all channels can be selected simultaneously. These registers affect the receive-side framer only. (MSB) CH8 CH16 CH24 (LSB) CH1 CH9 CH17 CH7 CH15 CH23 CH6 CH14 CH22 CH5 CH13 CH21 CH4 CH12 CH20 CH3 CH11 CH19 CH2 CH10 CH18 RBCS1 RBCS2 RBCS3 Register Name: Register Description: Register Address: Bit # Name Default 7 BSE8 0 RBBS Receive BERT Bit Suppress Register 08Bh 6 BSE7 0 5 BSE6 0 4 BSE5 0 3 BSE4 0 2 BSE3 0 1 BSE2 0 0 BSE1 0 Bit 0 / Receive Channel Bit 1 Suppress (BSE1). LSB of the channel. Set to one to stop this bit from being used. Bit 1 / Receive Channel Bit 2 Suppress (BSE2). Set to one to stop this bit from being used. Bit 2 / Receive Channel Bit 3 Suppress (BSE3). Set to one to stop this bit from being used. Bit 3 / Receive Channel Bit 4 Suppress (BSE4). Set to one to stop this bit from being used. Bit 4 / Receive Channel Bit 5 Suppress (BSE5). Set to one to stop this bit from being used Bit 5 / Receive Channel Bit 6 Suppress (BSE6). Set to one to stop this bit from being used. Bit 6 / Receive Channel Bit 7 Suppress (BSE7). Set to one to stop this bit from being used. Bit 7 / Receive Channel Bit 8 Suppress (BSE8). MSB of the channel. Set to one to stop this bit from being used. 103 DS26401 Octal T1/E1/J1 Framer 9. T1 TRANSMIT 9.1 T1 Transmit Register Map ADDRESS 100 101 102 103 104 105 106 107 108 109 10A 10B 10C 10D 10E 10F 110 111 112 113 114 115 116 117 118 119 11A 11B 11C 11D 11E 11F 120 121 122 123 124 125 126 127 128 129 12A 12B 12C 12D 12E 12F 130 131 132 133 134 135 136 TYPE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- R/W R/W -- R/W -- -- -- -- R/W R/W R/W -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W FUNCTION Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Tx HDLC Control 1 Tx HDLC Bit Suppress Unused Tx HDLC Control 2 Unused Unused Unused Unused Tx Software Signaling Insertion Enable 1 Tx Software Signaling Insertion Enable 2 Tx Software Signaling Insertion Enable 3 Unused Tx Test Register 1 Tx Test Register 2 Tx Test Register 3 Tx Test Register 4 Tx Idle Definition 1 Tx Idle Definition 2 Tx Idle Definition 3 Tx Idle Definition 4 Tx Idle Definition 5 Tx Idle Definition 6 Tx Idle Definition 7 Tx Idle Definition 8 Tx Idle Definition 9 Tx Idle Definition 10 Tx Idle Definition 11 Tx Idle Definition 12 Tx Idle Definition 13 Tx Idle Definition 14 Tx Idle Definition 15 Tx Idle Definition 16 Tx Idle Definition 17 Tx Idle Definition 18 Tx Idle Definition 19 Tx Idle Definition 20 Tx Idle Definition 21 Tx Idle Definition 22 Tx Idle Definition 23 NAME -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- THC1 THBSE -- THC2 -- -- -- -- SSIE1 SSIE2 SSIE3 -- TTEST1 TTEST2 TTEST3 TTEST4 TIDR1 TIDR2 TIDR3 TIDR4 TIDR5 TIDR6 TIDR7 TIDR8 TIDR9 TIDR10 TIDR11 TIDR12 TIDR13 TIDR14 TIDR15 TIDR16 TIDR17 TIDR18 TIDR19 TIDR20 TIDR21 TIDR22 TIDR23 PAGE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 248 249 -- 249 -- -- -- -- 121 121 121 -- -- -- -- -- 233 233 233 233 233 233 233 233 233 233 233 233 233 233 233 233 233 233 233 233 233 233 233 104 DS26401 Octal T1/E1/J1 Framer ADDRESS 137 138 139 13A 13B 13C 13D 13E 13F 140 141 142 143 144 145 146 147 148 149 14A 14B 14C 14D 14E 14F 150 151 152 153 154 155 156 157 158 159 15A 15B 15C 15D 15E 15F 160 161 162 163 164 165 166 167 168 169 16A 16B 16C 16D 16E 16F 170 171 172 173 TYPE R/W -- -- -- -- -- -- -- -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W -- -- -- -- R/W R/W R/W -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- R/W R/W R/W R/W R/W -- -- -- -- -- -- -- -- -- -- -- -- -- FUNCTION Tx Idle Definition 24 Unused Unused Unused Unused Unused Unused Unused Unused Tx Signaling 1 Tx Signaling 2 Tx Signaling 3 Tx Signaling 4 Tx Signaling 5 Tx Signaling 6 Tx Signaling 7 Tx Signaling 8 Tx Signaling 9 Tx Signaling 10 Tx Signaling 11 Tx Signaling 12 Unused Unused Unused Unused Tx Channel Idle Code Enable 1 Tx Channel Idle Code Enable 2 Tx Channel Idle Code Enable 3 Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Tx FDL Tx BOC Tx SLC96 Data Link 1 Tx SLC96 Data Link 2 Tx SLC96 Data Link 3 Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused NAME TIDR24 -- -- -- -- -- -- -- -- TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS12 -- -- -- -- TCICE1 TCICE2 TCICE3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TFDL TBOC TSLC1 TSLC2 TSLC3 -- -- -- -- -- -- -- -- -- -- -- -- -- PAGE 233 -- -- -- -- -- -- -- -- 231 231 231 231 231 231 231 231 231 231 231 231 -- -- -- -- 233 233 233 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 131 130 132 132 132 -- -- -- -- -- -- -- -- -- -- -- -- -- 105 DS26401 Octal T1/E1/J1 Framer ADDRESS 174 175 176 177 178 179 17A 17B 17C 17D 17E 17F 180 181 182 183 184 185 186 187 188 189 18A 18B 18C 18D 18E 18F 190 191 192 193 194 195 196 197 198 199 19A 19B 19C 19D 19E 19F 1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 1A9 1AA 1AB 1AC 1AD 1AE 1AF 1B0 TYPE -- -- -- -- -- -- -- -- -- -- -- -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W -- -- R/W R/W R/W R/W R/W -- -- -- -- -- -- -- -- -- -- -- -- R/W R/W R/W R/W -- -- -- -- -- -- -- -- -- R/W R/W -- -- -- FUNCTION Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Tx Master Mode Tx Control 1 Tx Control 2 Tx Control 3 Tx I/O Configuration Tx Elastic Store Control Tx Control 4 Tx HDLC FIFO Control Tx Interleave Bus Op Control Tx DS0 Monitor Select Tx BERT Interface Control Tx BERT Bit Suppress Enable Unused Unused Tx Synchronizer Control Tx Test Register 5 Tx Latched Status 1 Tx Latched Status 2 (HDLC) Tx Latched Status 3 (SYNC) Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Tx Interrupt Information Register Tx Interrupt Mask Register 1 Tx Interrupt Mask Register 2 (HDLC) Tx Interrupt Mask Register 3 (SYNC) Unused Unused Unused Unused Unused Unused Unused Unused Unused Tx Code Definition 1 Tx Code Definition 2 Unused Unused Unused NAME -- -- -- -- -- -- -- -- -- -- -- -- TMMR TCR1 TCR2 TCR3 TIOCR TESCR TCR4 THFC TIBOC TDS0SEL TBICR TBBS -- -- TSYNCC TTEST5 TLS1 TLS2 TLS3 -- -- -- -- -- -- -- -- -- -- -- -- TIIR TIM1 TIM2 TIM3 -- -- -- -- -- -- -- -- -- TCD1 TCD2 -- -- -- PAGE -- -- -- -- -- -- -- -- -- -- -- -- 217 219 220 222 224 237 113 250 257 229 146 -- -- -- 260 -- 226 252 261 -- -- -- -- -- -- -- -- -- -- -- -- 218 227 253 261 143 143 106 DS26401 Octal T1/E1/J1 Framer ADDRESS 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 1B9 1BA 1BB 1BC 1BD 1BE 1BF 1C0 1C1 1C2 1C3 1C4 1C5 1C6 1C7 1C8 1C9 1CA 1CB 1CC 1CD 1CE 1CF 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9 1DA 1DB 1DC 1DD 1DE 1DF 1E0-1FF TYPE R -- R W -- -- -- -- -- -- R -- -- -- -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W -- R/W R/W R/W -- -- -- -- -- -- -- -- -- -- FUNCTION Tx Real-Time Status Register 2 (HDLC) Unused Tx HDLC FIFO Buffer Available Tx HDLC FIFO Unused Unused Unused Unused Unused Unused Tx DS0 Monitor Unused Unused Unused Unused Tx Blank Channel Select 1 Tx Blank Channel Select 2 Tx Blank Channel Select 3 Tx Blank Channel Select 4 Tx Channel Blocking 1 Tx Channel Blocking 2 Tx Channel Blocking 3 Tx Channel Blocking 4 Tx Hardware Signaling Channel Select 1 Tx Hardware Signaling Channel Select 2 Tx Hardware Signaling Channel Select 3 Tx Hardware Signaling Channel Select 4 Tx Gapped Clock Channel Select 1 Tx Gapped Clock Channel Select 2 Tx Gapped Clock Channel Select 3 Tx Gapped Clock Channel Select 4 Per-Channel Loopback Enable 1 Per-Channel Loopback Enable 2 Per-Channel Loopback Enable 3 Unused Tx BERT Channel Select 1 Tx BERT Channel Select 2 Tx BERT Channel Select 3 Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused NAME TRTS2 -- TFBA THF -- -- -- -- -- -- TDS0M -- -- -- -- TBCS1 TBCS2 TBCS3 TBCS4 TCBR1 TCBR2 TCBR3 TCBR4 THSCS1 THSCS2 THSCS3 THSCS4 TGCCS1 TGCCS2 TGCCS3 TGCCS4 PCL1 PCL2 PCL3 -- TBPCS1 TBPCS2 TBPCS3 -- -- -- -- -- -- -- -- -- -- PAGE 251 140 140 119 238 238 238 238 234 234 234 234 232 232 232 232 239 239 239 239 118 118 118 Note: The register addresses are 9-bits wide (shown here in hexadecimal). Addresses with the MSB clear (0xxH) are used for the DS26401 receiver; addresses with the MSB set (1xxH) are used for the DS26401 transmitter. 107 DS26401 Octal T1/E1/J1 Framer 9.2 T1 Transmit Formatter Description and Operation Eight fully independent DS1/E1 transmit formatters are included within the DS26401. The formatters are designed to interface seamlessly to the line via an external LIU. Each port can be individually programmed to transmit AMI, B8ZS, HDB3, or NRZ data. In T1 mode each formatter supports D4 (SF), ESF, and SLC-96 frame formats, and transmits common alarms such as AIS, RAI, AIS-CI, and RAI-CI. Each framer also has an HDLC controller which can be mapped into a single time slot, or Sa4 to Sa8 bits (E1 Mode) or the FDL (T1 Mode) and has 64 byte FIFO buffers in both the transmit and receive paths. The user can select any specific bits within the time slot(s) to assign to the HDLC controllers, as well as specific Sa bits (E1 Mode). The HDLC controllers perform all the necessary overhead for generating and receiving Performance Report Messages (PRM) as described in ANSI T1.403 and the messages as described in AT&T TR54016. The controllers automatically generate and detects flags, generate and check the CRC check sum, generate and detect abort sequences, stuff and de-stuff zeros, and byte align to the data stream. The large FIFO buffers allow a full PRM to be received or transmitted without host intervention. Other features contained within each framer include a BOC generator and a 16-bit loop code generator. Host interface is simplified with status registers optimized for either interrupt driven or polled environments. In many cases, status bits are reported both real-time and latched on change-of-state with separate bits for each state change. Most latched bits can be enabled to generate an external interrupt on the INT pin. Additional details concerning the operation of the DS1 formatter are included within the register descriptions within this section. 108 DS26401 Octal T1/E1/J1 Framer 9.3 Transmit-Master Mode Register The transmit-master mode register (TMMR) controls the initialization of the transmit-side formatter. The FRM_EN bit may be left `low' if the formatter for that particular port is not going to be used, putting the circuit in a low-power (sleep) state. Register Name: Register Description: Register Address: TMMR Transmit Master Mode Register 180h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 Bit # Name Default 7 FRM_EN 0 6 INIT_DONE 0 5 -- 0 4 -- 0 3 -- 0 2 -- 0 1 SFTRST 0 0 T1/E1 0 Bit 0 / Transmitter T1/E1 Mode Select (T1/E1). Sets operating mode for transmitter only! This bit must be written with the desired value prior to setting INIT_DONE. 0 = T1 operation 1 = E1 operation Bit 1 / Soft Reset (SFTRST). Level-sensitive processor reset. Should be taken high then low to reset and initialize the internal processor. 0 = Normal operation 1 = Hold the internal RISC in reset. This bit only affects the transmit-side processor. Bits 2-5 / Unused. Must be set = 0 for proper operation. Bit 6 / Initialization Done (INIT_DONE). The host (user) must set this bit once he/she has written the configuration registers. The host is required to write or clear all RAM based registers (addresses 100H to 17FH) prior to setting this bit. Once INIT_DONE is set, the internal processor will check the FRM_EN bit. If enabled, the internal processor continues executing based on the initial configuration. Bit 7 / Framer Enable (FRM_EN). This bit must be written with the desired value prior to setting INIT_DONE. 0 = Framer disabled (held in low-power state) 1 = Framer enabled (all features active) 9.4 Interrupt Information Registers The interrupt information registers provide an indication of which DS26401 status registers are generating an interrupt. When an interrupt occurs, the host can read TIIR to quickly identify which of the transmit status registers are causing the interrupt(s). These are real-time registers in that the bits will clear once the appropriate interrupt has been serviced and cleared. Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 TIIR Transmit Interrupt Information Register 19Fh + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 TLS3 0 1 TLS2 0 0 TLS1 0 109 DS26401 Octal T1/E1/J1 Framer 9.5 T1 Transmit Control Registers Register Name: Register Description: Register Address: Bit # Name Default 7 TJC 0 TCR1 Transmit Control Register 1 181h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 TFPT 0 5 TCPT 0 4 TSSE 0 3 GB7S 0 2 TB8ZS 0 1 TAIS 0 0 TRAI 0 Bit 0 / Transmit Remote Alarm Indication (TRAI) 0 = do not transmit remote alarm 1 = transmit remote alarm Bit 1 / Transmit Alarm Indication Signal (TAIS) 0 = transmit data normally 1 = transmit an unframed all-ones code at TPOS and TNEG Bit 2 / Transmit B8ZS Enable (TB8ZS) 0 = B8ZS disabled 1 = B8ZS enabled Bit 3 / Global Bit 7 Stuffing (GB7S) 0 = allow the SSIEx registers to determine which channels containing all zeros are to be bit 7 stuffed 1 = force bit 7 stuffing in all-zero byte channels regardless of how the SSIEx registers are programmed Bit 4 / Transmit-Software Signaling Enable (TSSE) 0 = do not source signaling data from the TSx registers regardless of the SSIEx registers. The SSIEx registers still define which channels are to have B7 stuffing performed. 1 = source signaling data as enabled by the SSIEx registers. Bit 5 / Transmit CRC Pass-Through (TCPT) 0 = source CRC6 bits internally 1 = CRC6 bits sampled at TSER during F-bit time Bit 6 / Transmit F-Bit Pass-Through (TFPT) 0 = F bits sourced internally 1 = F bits sampled at TSER Bit 7 / Transmit Japanese CRC6 Enable (TJC) 0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation) 1 = use Japanese standard JT-G704 CRC6 calculation 110 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 TFDLS 0 TCR2 Transmit Control Register 2 182h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 TSLC96 0 5 -- 0 4 FBCT2 0 3 FBCT1 0 2 TD4RM 0 1 PDE 0 0 TB7ZS 0 Bit 0 / Transmit Side Bit 7 Zero Suppression Enable (TB7ZS) 0 = no stuffing occurs 1 = force bit 7 to a one as determined by the GB7S bit at TCR1.3 Bit 1 / Pulse Density Enforcer Enable (PDE). The framer always examines both the transmit and receive data streams for violations of the following rules which are required by ANSI T1.403: no more than 15 consecutive zeros and at least N ones in each and every time window of 8 x (N +1) bits where N = 1 through 23. Violations for the transmit and receive data streams are reported in the TLS1.3 and RLS2.7 bits respectively. When this bit is set to one, the DS26401 will force the transmitted stream to meet this requirement no matter the content of the transmitted stream. When running B8ZS, this bit should be set to zero since B8ZS encoded data streams cannot violate the pulse density requirements. 0 = disable transmit pulse density enforcer 1 = enable transmit pulse density enforcer Bit 2 / Transmit D4 RAI Select (TD4RM) 0 = zeros in bit 2 of all channels 1 = a one in the S-bit position of frame 12 Bit 3 / F Bit Corruption Type 1. (FBCT1). A low-to-high transition of this bit causes the next three consecutive Ft (D4 framing mode) or FPS (ESF framing mode) bits to be corrupted causing the remote end to experience a loss of synchronization. Bit 4 / F Bit Corruption Type 2. (FBCT2). Setting this bit high enables the corruption of one Ft (D4 framing mode) or FPS (ESF framing mode) bit in every 128 Ft or FPS bits as long as the bit remains set. Bit 5 / Unused. Must be set = 0 for proper operation. Bit 6 / Transmit SLC-96 (TSLC96). Set this bit to a one in SLC-96 framing applications. Must be set to source the SLC-96 alignment pattern and data from the TSLC1-3 registers. See Section 8.12 for details. 0 = SLC-96 insertion disabled 1 = SLC-96 insertion enabled Bit 7 / TFDL Register Select (TFDLS) 0 = source FDL or Fs bits from the internal TFDL register or the SLC-96 data formatter (TCR2.6) 1 = source FDL or Fs bits from the internal HDLC controller 111 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 ODF 0 TCR3 Transmit Control Register 3 183h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 ODM 0 5 TCSS1 0 4 TCSS0 0 3 MFRS 0 2 TFM 0 1 IBVD 0 0 TLOOP 0 Bit 0 / Transmit Loop-Code Enable (TLOOP). See Section 8.13 for details. 0 = transmit data normally 1 = replace normal transmitted data with repeating code as defined in registers TCD1 and TCD2 Bit 1 / Insert BPV (IBPV). A 0-to-1 transition on this bit will cause a single BiPolar Violation (BPV) to be inserted into the transmit data stream. Once this bit has been toggled from a 0 to a 1, the device waits for the next occurrence of three consecutive ones to insert the BPV. This bit must be cleared and set again for a subsequent error to be inserted. Bit 2 / Transmit Frame Mode Select (TFM) 0 = ESF framing mode 1 = D4 framing mode Bit 3 / Multiframe Reference Select (MFRS). This bit selects the source for the transmit formatter multiframe boundary. 0 = Normal Operation. Transmit multiframe boundary is determined by 'line-side' counters referenced to TSYNC when TSYNC is an input. Free running when TSYNC is an output. 1 = Pass-Forward Operation. Tx multiframe boundary determined by 'system-side' counters referenced to TSSYNC input, which is then 'passed forward' to the line side clock domain. This mode can only be used when the transmit elastic store is enabled with a synchronous backplane (i.e., no frame slips allowed). This mode must be used to allow Tx hardware signaling insertion while the Tx elastic store is enabled. Bit 4 / Transmit Clock Source Select Bit 0 (TCSS0) Bit 5 / Transmit Clock Source Select Bit 1 (TCSS1) TCSS1 0 0 1 1 TCSS0 0 1 0 1 Transmit Clock Source The TCLK pin is always the source of Transmit Clock. Switch to the clock present at RCLK when the signal at the TCLK pin fails to transition after 1 channel time. For Future Use Use the signal present at RCLK as the Transmit Clock. The TCLK pin is ignored. Bit 6 / Output Data Mode (ODM) 0 = pulses at TPOS and TNEG are one full TCLK period wide 1 = pulses at TPOS and TNEG are 1/2 TCLK period wide Bit 7 / Output Data Format (ODF) 0 = bipolar data at TPOS and TNEG 1 = NRZ data at TPOS; TNEG = 0 112 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 TCR4 Transmit Control Register 4 186h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 -- 0 4 -- 0 3 TRAIM 0 2 TAISM 0 1 TC1 0 0 TC0 0 Bits 0 to 1 / Transmit Code Length Definition Bits (TC0 to TC1) TC1 0 0 1 1 TC0 0 1 0 1 Length Selected (bits) 5 6/3 7 16 / 8 / 4 / 2 / 1 Bit 2 / Transmit AIS Mode (TAISM). Determines the pattern sent when TAIS (TCR1.1) is activated. 0 = transmit normal AIS (unframed all ones) upon activation with TCR1.1 1 = transmit AIS-CI (T1.403) upon activation with TCR1.1 Bit 3 / Transmit RAI Mode (TRAIM). Determines the pattern sent when TRAI (TCR1.0) is activated in ESF frame mode only. 0 = transmit normal RAI upon activation with TCR1.0 1 = transmit RAI-CI (T1.403) upon activation with TCR1.0 Bits 4-7 / Unused. Must be set = 0 for proper operation. 113 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 TCLKINV 0 TIOCR Transmit I/O Configuration Register 184h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 TSYNCINV 0 5 TSSYNCINV 0 4 TSCLKM 0 3 TSSM 0 2 TSIO 0 1 TSDW 0 0 TSM 0 Bit 0 / TSYNC Mode Select (TSM). Selects frame or multiframe mode for the TSYNC pin. 0 = frame mode 1 = multiframe mode Bit 1 / TSYNC Doublewide (TSDW). (Note: This bit must be set to zero when TSM = 1 or when TSIO = 0.) 0 = do not pulse double wide in signaling frames 1 = do pulse double wide in signaling frames Bit 2 / TSYNC I/O Select (TSIO) 0 = TSYNC is an input 1 = TSYNC is an output Bit 3 / TSSYNC Mode Select (TSSM). Selects frame or multiframe mode for the TSSYNC pin. 0 = frame mode 1 = multiframe mode Bit 4 / TSYSCLK Mode Select (TSCLKM) 0 = if TSYSCLK is 1.544MHz 1 = if TSYSCLK is 2.048/4.096/8.192/16.384MHz or IBO enabled (see Section 9.20 for details on IBO function) Bit 5 / TSSYNC Invert (TSSYNCINV) 0 = No inversion 1 = Invert Bit 6 / TSYNC Invert (TSYNCINV) 0 = No inversion 1 = Invert Bit 7 / TCLK Invert (TCLKINV) 0 = No inversion 1 = Invert 114 DS26401 Octal T1/E1/J1 Framer 9.6 T1 Transmit Status and Information When a particular event has occurred (or is occurring), the appropriate bit in one of these registers will be set to a one. Status bits may operate in either a latched or real-time fashion. Some latched bits may be enabled to generate a hardware interrupt via the INT signal. Real-Time Bits Some status bits operate in a real-time fashion. These bits are read-only and indicate the present state of an alarm or a condition. Real time bits will remain stable, and valid during the host read operation. The current value of the internal status signals can be read at any time from the real time status registers without changing any the latched status register bits Latched Bits When an event or an alarm occurs and a latched bit is set to a one, it will remain set until cleared by the user. These bits typically respond on a `change-of-state' for an alarm, condition, or event; and operate in a read-thenwrite fashion. The user should read the value of the desired status bit, and then write a `1' to that particular bit location in order to clear the latched value (write a `0' to locations not to be cleared). Once the bit is cleared, it will not be set again until the event has occurred again. Mask Bits Some of the alarms and events can be either masked or unmasked from the interrupt pin via the Interrupt Mask Registers (TIMx). When unmasked, the INT signal will be forced low when the enabled event or condition occurs. The INT pin will be allowed to return high (if no other unmasked interrupts are present) when the user reads then clears (with a write) the alarm bit that caused the interrupt to occur. Note that the latched status bit and the INT pin will clear even if the alarm is still present. 115 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 TESF 0 TLS1 Transmit Latched Status Register 1 190h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 TESEM 0 5 TSLIP 0 4 TSLC96 0 3 TPDV 0 2 TMF 0 1 LOTCC 0 0 LOTC 0 All bits in this register are latched and can cause interrupts. Bit 0 / Loss of Transmit Clock Condition (LOTC). Set when the TCLK pin has not transitioned for approximately 3 clock periods. Will force the LOTC pin high if enabled. This bit can be cleared by the host even if the condition is still present. The LOTC pin will remain high while the condition exists, even if the host has cleared the status bit. If enabled by TIM1.0, the INT pin will transition low when this bit is set, and transition high when this bit is cleared (if no other unmasked interrupt conditions exist). Bit 1 / Loss of Transmit Clock Condition Clear (LOTCC). Set when the LOTC condition has cleared (a clock has been sensed at the TCLK pin). Bit 2 / Transmit Multiframe Event (TMF). Set every 1.5ms on D4 MF boundaries or every 3ms on ESF MF boundaries. Bit 3 / Transmit Pulse Density Violation Event (TPDV). Set when the transmit data stream does not meet the ANSI T1.403 requirements for pulse density. Bit 4 / Transmit SLC96 Multiframe Event (TSLC96). When enabled by TCR2.6, this bit will set once per SLC96 multiframe (72 frames) to alert the host that new data may be written to the TSLC1-TSLC3 registers. See section 9.16. Bit 5 / Transmit Elastic Store Slip Occurrence Event (TSLIP). Set when the transmit elastic store has either repeated or deleted a frame. Bit 6 / Transmit Elastic Store Empty Event (TESEM). Set when the transmit elastic store buffer empties and a frame is repeated. Bit 7 / Transmit Elastic Store Full Event (TESF). Set when the transmit elastic store buffer fills and a frame is deleted. 116 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 TESF 0 TIM1 Transmit Interrupt Mask Register 1 1A0h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 TESEM 0 5 TSLIP 0 4 TSLC96 0 3 TPDV 0 2 TMF 0 1 LOTCC 0 0 LOTC 0 Bit 0 / Loss of Transmit Clock Condition (LOTC) 0 = interrupt masked 1 = interrupt enabled Bit 1 / Loss of Transmit Clock Clear Condition (LOTCC) 0 = interrupt masked 1 = interrupt enabled Bit 2 / Transmit Multiframe Event (TMF) 0 = interrupt masked 1 = interrupt enabled Bit 3 / Transmit Pulse Density Violation Event (TPDV) 0 = interrupt masked 1 = interrupt enabled Bit 4 / Transmit SLC96 Multiframe Event (TSLC96) 0 = interrupt masked 1 = interrupt enabled Bit 5 / Transmit Elastic Store Slip Occurrence Event (TSLIP) 0 = interrupt masked 1 = interrupt enabled Bit 6 / Transmit Elastic Store Empty Event (TESEM) 0 = interrupt masked 1 = interrupt enabled Bit 7 / Transmit Elastic Store Full Event (TESF) 0 = interrupt masked 1 = interrupt enabled 117 DS26401 Octal T1/E1/J1 Framer 9.7 T1 Per-Channel Loopback The Per-Channel Loopback Registers (PCLRs) determine which channels (if any) from the backplane should be replaced with the data from the receive side or in other words, off of the T1 or E1 line. If this loopback is enabled, then transmit and receive clocks and frame syncs must be synchronized. One method to accomplish this would be to tie RCLK to TCLK and RFSYNC to TSYNC. There are no restrictions on which channels can be looped back or on how many channels can be looped back. Each of the bit position in the Per-Channel Loopback Registers (PCLR1/PCLR2/PCLR3) represent a DS0 channel in the outgoing frame. When these bits are set to a one, data from the corresponding receive channel will replace the data on TSER for that channel. Register Name: Register Description: Register Address: (MSB) CH8 CH16 CH24 PCL1, PCL2, PCL3 Per-Channel Loopback Enable Registers 1D0h, 1D1h, 1D2h [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8] (LSB) CH1 CH9 CH17 CH7 CH15 CH23 CH6 CH14 CH22 CH5 CH13 CH21 CH4 CH12 CH20 CH3 CH11 CH19 CH2 CH10 CH18 PCL1 PCL2 PCL3 Bits 0 to 7 / Per-Channel Loopback Enable for Channels 1 to 24 (CH1 to CH24) 0 = Loopback disabled 1 = Enable Loopback. Source data from the corresponding receive channel 118 DS26401 Octal T1/E1/J1 Framer 9.8 T1 Transmit DS0 Monitoring Function The DS26401 has the ability to monitor one DS0 (64kbps) channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction the user will determine which channel is to be monitored by properly setting the TCM0 to TCM4 bits in the TDS0SEL register. In the receive direction, the RCM0 to RCM4 bits in the RDS0SEL register need to be properly set. The DS0 channel pointed to by the TCM0 to TCM4 bits will appear in the Transmit DS0 Monitor (TDS0M) register and the DS0 channel pointed to by the RCM0 to RCM4 bits will appear in the Receive DS0 (RDS0M) register. The TCM4 to TCM0 and RCM4 to RCM0 bits should be programmed with the decimal decode of the appropriate T1or E1 channel. T1 channels 1 through 24 map to register values 0 through 23. E1 channels 1 through 32 map to register values 0 through 31. For example, if DS0 channel 6 in the transmit direction and DS0 channel 15 in the receive direction needed to be monitored, then the following values would be programmed into TDS0SEL and RDS0SEL: TCM4 = 0 TCM3 = 0 TCM2 = 1 TCM1 = 0 TCM0 = 1 Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 RCM4 = 0 RCM3 = 1 RCM2 = 1 RCM1 = 1 RCM0 = 0 TDS0SEL Transmit DS0 Channel Monitor Select 189h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 -- 0 4 TCM4 0 3 TCM3 0 2 TCM2 0 1 TCM1 0 0 TCM0 0 Bits 0 to 4 / Transmit Channel Monitor Bits (TCM0 to TCM4). TCM0 is the LSB of a 5 bit channel select that determines which transmit channel data will appear in the TDS0M register. Bits 5 to 7 / Unused. Must be set = 0 for proper operation. Register Name: Register Description: Register Address: Bit # Name Default 7 B1 0 TDS0M Transmit DS0 Monitor Register 1BBh + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 B2 0 5 B3 0 4 B4 0 3 B5 0 2 B6 0 1 B7 0 0 B8 0 Bits 0 to 7 / Transmit DS0 Channel Bits (B1 to B8). Transmit channel data that has been selected by the Transmit Channel Monitor Select Register. B8 is the LSB of the DS0 channel (last bit to be transmitted). 119 DS26401 Octal T1/E1/J1 Framer 9.9 T1 Transmit Signaling Operation There are two methods to provide transmit signaling data--processor-based (i.e., software-based) or hardwarebased. Processor-based refers to access through the transmit-signaling registers, TS1-TS12, while hardwarebased refers to using the TSIG pins. Both methods can be used simultaneously. 9.9.1 Processor-Based Mode In Processor Based mode, signaling data is loaded into the Transmit Signaling registers (TS1 - TS12) via the host interface. On multiframe boundaries, the contents of these registers is loaded into a shift register for placement in the appropriate bit position in the outgoing data stream. The user can utilize the Transmit Multiframe Interrupt in Latched Status Register 1 (TLS1.2) to know when to update the signaling bits. The user need not update any transmit signaling register for which there is no change of state for that register. Each Transmit Signaling Register contains the Robbed Bit signaling for each time slots that will be inserted into the outgoing stream if enabled to do so via TCR1.4. Signaling data can be sourced from the TS registers on a per-channel basis by utilizing the Software Signaling Insertion Enable registers, SSIE1 through SSIE3. In T1 ESF framing mode, there are four signaling bits per channel (A, B, C, and D). TS1 - TS12 contain a full multiframe of signaling data. In T1 D4 framing mode, there are only two signaling bits per channel (A and B). In T1 D4 framing mode, the framer uses A and B bit positions for the next multiframe. The C and D bit positions become `don't care' in D4 mode. 9.9.2 Hardware-Based Mode In hardware-based mode, signaling data is input via the TSIG pin. This signaling PCM stream is buffered and inserted to the data stream being input at the TSER pin. Signaling data may be input via the Transmit Hardware Signaling Channel Select (THSCS) function, the framer can be set up to take the signaling data presented at the TSIG pin and insert the signaling data into the PCM data stream that is being input at the TSER pin. The user can control which channels are to have signaling data from the TSIG pin inserted into them on a per-channel basis. The signaling insertion capabilities of the framer are available whether the transmit side elastic store is enabled or disabled. If the elastic store is enabled, the backplane clock (TSYSCLK) can be either 1.544MHz or 2.048MHz. If IBO mode is enabled, then TSYSCLK may also be 4.096MHz, 8.192MHz, or 16.384MHz. 120 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: (MSB) CH1-A CH2-A CH3-A CH4-A CH5-A CH6-A CH7-A CH8-A CH9-A CH10-A CH11-A CH12-A TS1 TO TS12 Transmit Signaling Registers (T1 MODE) 140h - 14Bh [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8] (LSB) CH13-D CH14-D CH15-D CH16-D CH17-D CH18-D CH19-D CH20-D CH21-D CH22-D CH23-D CH24-D CH1-B CH2-B CH3-B CH4-B CH5-B CH6-B CH7-B CH8-B CH9-B CH10-B CH11-B CH12-B CH1-C CH2-C CH3-C CH4-C CH5-C CH6-C CH7-C CH8-C CH9-C CH10-C CH11-C CH12-C CH1-D CH2-D CH3-D CH4-D CH5-D CH6-D CH7-D CH8-D CH9-D CH10-D CH11-D CH12-D CH13-A CH14-A CH15-A CH16-A CH17-A CH18-A CH19-A CH20-A CH21-A CH22-A CH23-A CH24-A CH13-B CH14-B CH15-B CH16-B CH17-B CH18-B CH19-B CH20-B CH21-B CH22-B CH23-B CH24-B CH13-C CH14-C CH15-C CH16-C CH17-C CH18-C CH19-C CH20-C CH21-C CH22-C CH23-C CH24-C TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS12 Note: In D4 framing mode, the C and D bits are not used. Register Name: Register Description: Register Address: (MSB) CH8 CH16 CH24 SSIE1, SSIE2, SSIE3 Software Signaling Insertion Enable Registers 118h, 119h, 11Ah [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8] (LSB) CH1 CH9 CH17 CH7 CH15 CH23 CH6 CH14 CH22 CH5 CH13 CH21 CH4 CH12 CH20 CH3 CH11 CH19 CH2 CH10 CH18 SSIE1 SSIE2 SSIE3 Bits 0 to 7 / Software Signaling Insertion Enable for Channels 1 to 24 (SSIEx). These bits determine which channels are to have signaling inserted form the Transmit Signaling registers. 0 = do not source signaling data from the TS registers for this channel 1 = source signaling data from the TS registers for this channel 121 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: THSCS1, THSCS2, THSCS3, THSCS4 Transmit Hardware Signaling Channel Select Registers 1C8h, 1C9h, 1CAh, 1CBh [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8] (LSB) CH1 CH9 CH17 CH25 (MSB) CH8 CH16 CH24 CH32 CH7 CH15 CH23 CH31 CH6 CH14 CH22 CH30 CH5 CH13 CH21 CH29 CH4 CH12 CH20 CH28 CH3 CH11 CH19 CH27 CH2 CH10 CH18 CH26 THSCS1 THSCS2 THSCS3 THSCS4* Bits 0 to 7 / Transmit Hardware Signaling Channel Select for Channels 1 to 32 (THSCS1-4). These bits determine which channels have signaling data inserted from the TSIG pin into the TSER PCM data. 0 = do not source signaling data from the TSIG pin for this channel 1 = source signaling data from the TSIG pin for this channel * Note that THSCS4 is only used in 2.048MHz backplane applications. 122 DS26401 Octal T1/E1/J1 Framer 9.10 T1 Transmit Per-Channel Idle Code Insertion Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions. Twenty-four Transmit Idle Definition Registers (TIDR1-TIDR24) are provided to set the 8-bit idle code for each channel. The Transmit Channel Idle Code Enable registers (TCICE1-3) are used to enable idle code replacement on a per channel basis. Register Name: Register Description: Register Address: Bit # Name Default 7 C7 0 TIDR1 to TIDR24 Transmit Idle Code Definition Registers 1 to 24 120h to 137h [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8] 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Bits 0 to 7 / Per-Channel Idle Code Bits (C0 to C7). C0 is the LSB of the Code (this bit is transmitted last). Address 120H is for channel 1, address 137H is for channel 24. The Transmit Channel Idle Code Enable Registers (TCICE1/2/3) are used to determine which of the 24 T1 channels from the backplane should be overwritten with the code placed in the Transmit Idle Code Definition Register. Register Name: Register Description: Register Address: (MSB) CH8 CH16 CH24 TCICE1, TCICE2, TCICE3 Transmit Channel Idle Code Enable Registers 150h, 151h, 152h [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8] (LSB) CH1 CH9 CH17 CH7 CH15 CH23 CH6 CH14 CH22 CH5 CH13 CH21 CH4 CH12 CH20 CH3 CH11 CH19 CH2 CH10 CH18 TCICE1 TCICE2 TCICE3 Bits 0 to 7 / Transmit Channels 1 to 24 Code Insertion Control Bits (CH1 to CH24) 0 = do not insert data from the Idle Code Array into the transmit data stream 1 = insert data from the Idle Code Array into the transmit data stream 123 DS26401 Octal T1/E1/J1 Framer 9.11 T1 Transmit Channel Blocking Registers The Receive Channel blocking Registers (RCBR1 / RCBR2 / RCBR3 / RCBR4) and the Transmit Channel Blocking Registers (TCBR1 / TCBR2 / TCBR3 / TCHR4) control RCHBLK and TCHBLK pins respectively. The RCHBLK and TCHBLK pins are user programmable outputs that can be forced either high or low during individual channels. When the appropriate bits are set to a one, the RCHBLK and TCHBLK pin will be held high during the entire corresponding channel time. Register Name: Register Description: Register Address: TCBR1, TCBR2, TCBR3, TCBR4 Transmit Channel Blocking Registers 1C4h, 1C5h, 1C6h, 1C7h [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8] (LSB) CH1 CH9 CH17 CH25/Fbit (MSB) CH8 CH16 CH24 CH32 CH7 CH15 CH23 CH31 CH6 CH14 CH22 CH30 CH5 CH13 CH21 CH29 CH4 CH12 CH20 CH28 CH3 CH11 CH19 CH27 CH2 CH10 CH18 CH26 TCBR1 TCBR2 TCBR3 TCBR4* Bits 0 to 7 / Transmit Channels 1 to 32 Channel Blocking Control Bits (CH1 to CH32) 0 = force the TCHBLK pin to remain low during this channel time 1 = force the TCHBLK pin high during this channel time In T1 mode, the LSB of TCBR4 determines whether or not the TCHBLK signal will pulse high during the F-Bit time: TCBR4.0 = 0, do not pulse TCHBLK during the F-Bit TCBR4.0 = 1, pulse TCHBLK during the F-Bit In this mode, TCBR4.1 to TCBR4.7 should be set to 0. 124 DS26401 Octal T1/E1/J1 Framer 9.12 T1 Transmit Elastic Stores Operation The DS26401 contains dual two-frame elastic stores, one for the receive direction and one for the transmit direction. Both elastic stores are fully independent. The transmit- and receive-side elastic stores can be enabled/disabled independent of each other. Also, each elastic store can interface to either a 1.544MHz or 2.048/4.096/8.192/16.384MHz backplane without regard to the backplane rate of the other elastic store. The elastic stores have two main purposes. First, they can be used for rate conversion. When the DS26401 is in the T1 mode, the elastic stores can rate convert the T1 data stream to a 2.048MHz backplane. In E1 mode, the elastic store can rate convert the E1 data stream to a 1.544MHz backplane. Secondly, they can be used to absorb the differences in frequency and phase between the T1 or E1 data stream and an asynchronous (i.e., not locked) backplane clock (which can be 1.544MHz or 2.048MHz). In this mode, the elastic stores will manage the rate difference and perform controlled slips, deleting or repeating frames of data in order to manage the difference between the network and the backplane. The elastic stores can also be used to multiplex T1 or E1 data streams into higher backplane rates. This is the Interleave Bus Option (IBO) which is discussed in Section 9.20. Note that the receive elastic store status bits are contained in TLS1 with the associated interrupt bits located in TIM1. These bits indicate a receive slip event, or when the e-store FIFO is in a `full' or `empty' condition. See the register definition for TLS1 for additional information. The operation of the transmit elastic store is very similar to the receive side. If the transmit side elastic store is enabled a 1.544MHz or 2.048MHz clock can be applied to the TSYSCLK input. For higher rate system clock applications, see the Interleave Bus Option section. Controlled slips in the transmit elastic store are reported in the TLS1.5 bit and the direction of the slip is reported in the TLS1.6 and TLS1.7 bits. If the user selects to apply a 2.048MHz clock to the TSYSCLK pin, then the data input at TSER will be ignored on the channels marked by the TBCS registers. The user can supply frame or multiframe sync pulse to the TSSYNC input. Note that the user may find it useful to program the TCHBLK output as a method to mark backplane channels that will be ignored during T1 to E1 conversion. 125 DS26401 Octal T1/E1/J1 Framer 9.12.1 Elastic Stores Initialization There are two elastic store initializations that may be used to improve performance in certain applications, Elastic Store Reset and Elastic Store Align. Both of these involve the manipulation of the elastic store's read and write pointers and are useful primarily in synchronous applications (RSYSCLK/TSYSCLK are locked to RCLK/TCLK, respectively). The elastic store reset is used to minimize the delay through the elastic store. The elastic store align bit is used to center the read/write pointers to the extent possible. Elastic Store Delay After Initialization INITIALIZATION Receive Elastic Store Reset Transmit Elastic Store Reset Receive Elastic Store Align Transmit Elastic Store Align N = 9 for TSZS = 0 N = 2 for TSZS = 1 REGISTER BIT RESCR.2 TESCR.2 RESCR.3 TESCR.3 DELAY N bytes < Delay < 1 Frame + N bytes N bytes < Delay < 1 Frame + N bytes 1/2 Frame < Delay < 1 1/2 Frames 1/2 Frame < Delay < 1 1/2 Frames 9.12.2 Minimum Delay Mode Elastic store minimum delay mode may be used when the elastic store's system clock is locked to its network clock (i.e., RCLK locked to RSYSCLK for the receive side and TCLK locked to TSYSCLK for the transmit side). TESCR.1 and RESCR.1 enable the transmit and receive elastic store minimum delay modes. When enabled the elastic stores will be forced to a maximum depth of 32 bits instead of the normal two-frame depth. This feature is useful primarily in applications that interface to a 2.048MHz bus. Certain restrictions apply when minimum delay mode is used. In addition to the restriction mentioned above, RSYNC must be configured as an output when the receive elastic store is in minimum delay mode and TSYNC must be configured as an output when transmit minimum delay mode is enabled. The RSYNC and TSYNC outputs are registered on the rising edge of RSYSCLK and TSYSCLK respectfully. In a typical application RSYSCLK and TSYSCLK are locked to RCLK, and RSYNC (frame output mode) is connected to TSSYNC (frame input mode). All the slip contention logic in the framer is disabled (since slips cannot occur). On power-up after the RSYSCLK and TSYSCLK signals have locked to their respective network clock signals, the elastic store reset bits (TESCR.2 and RESCR.2) should be toggled from a zero to a one to ensure proper operation. 126 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 TDATFMT TESCR Transmit Elastic Store Control Register 185h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 TGCLKEN 5 -- 4 TSZS 3 TESALGN 2 TESR 1 TESMDM 0 TESE 0 0 0 0 0 0 0 0 Bit 0 / Transmit Elastic Store Enable (TESE) 0 = elastic store is bypassed 1 = elastic store is enabled Bit 1 / Transmit Elastic Store Minimum Delay Mode (TESMDM) 0 = elastic stores operate at full two frame depth 1 = elastic stores operate at 32-bit depth Bit 2 / Transmit Elastic Store Reset (TESR). Setting this bit from a zero to a one will force the read pointer into the same frame that the write pointer is exiting, minimizing the delay through the elastic store. If this command should place the pointers within the slip zone (see bit 4), then an immediate slip will occur and the pointers will move back to opposite frames. Should be toggled after TSYSCLK has been applied and is stable. Do not leave this bit set HIGH. Bit 3 / Transmit Elastic Store Align (TESALGN). Setting this bit from a zero to a one will force the transmit elastic store's write/read pointers to a minimum separation of half a frame. No action will be taken if the pointer separation is already greater or equal to half a frame. If pointer separation is less than half a frame, the command will be executed and the data will be disrupted. Should be toggled after TSYSCLK has been applied and is stable. Must be cleared and set again for a subsequent align. Bit 4 / Transmit Slip Zone Select (TSZS). This bit determines the minimum distance allowed between the elastic store read and write pointers before forcing a controlled slip. This bit is only applies during T1 to E1 or E1 to T1 conversion applications. 0 = force a slip at 9 bytes or less of separation (used for clustered blank channels) 1 = force a slip at 2 bytes or less of separation (used for distributed blank channels) Bit 5 / Unused. Must be set = 0 for proper operation. Bit 6 / Transmit Gapped Clock Enable (TGPCKEN) 0 = TCHCLK functions normally 1 = Enable gapped bit clock output on TCHCLK Bit 7 / Transmit Channel Data Format (TDATFMT) 0 = 64KBps (data contained in all 8 bits) 1 = 56KBps (data contained in 7 out of the 8 bits) Note: Bits 6 and 7 for fractional backplane support. See Section 9.13. 127 DS26401 Octal T1/E1/J1 Framer 9.12.3 Mapping T1 Channels from a 2.048MHz Backplane Setting the TSCLKM bit in TIOCR.4 will enable the transmit elastic store to operate with a 2.048MHz backplane (32 time slots/frame). In this mode, the user can chose which of the backplane channels on TSER will be mapped into the T1 data stream by programming the Transmit Blank Channel Select registers (TBCS1-4). A logic 1 in the associated bit location will force the transmit elastic store to ignore backplane data for that channel. Typically, the user will want to program eight channels to be ignored. The default (power-up) configuration will ignore channels 25 to 32, so that the first 24 backplane channels are mapped into the T1 transmit data stream. For example, if the user desired to transmit data from the 2.048MHz backplane channels 2-16 and 18-26, the TBCS registers should be programmed as follows: TBCS1 = 01h // ignore backplane channel 1 // TBCS2 = 00h TBCS3 = 01h // ignore backplane channel 17 // TBCS4 = FCh // ignore backplane channels 27-32 // Register Name: Register Description: Register Address: (MSB) CH8 CH16 CH24 CH32 TBCS1, TBCS2, TBCS3, TBCS4 Transmit Blank Channel Select Registers 1C0h, 1C1h, 1C2h, 1C3h [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8] (LSB) CH1 CH9 CH17 CH25 CH7 CH15 CH23 CH31 CH6 CH14 CH22 CH30 CH5 CH13 CH21 CH29 CH4 CH12 CH20 CH28 CH3 CH11 CH19 CH27 CH2 CH10 CH18 CH26 TBCS1 TBCS2 TBCS3 TBCS4 Bits 0 to 7 / Transmit Blank Channel Select for Channels 1 to 32 (TBCS1 to 32) 0 = transmit TSER data from this channel 1 = ignore TSER data from this channel Note that when two or more sequential channels are chosen to be ignored, the receive slip zone select bit should be set to zero. If the ignore channels are distributed (such as 1, 5, 9, 13, 17, 21, 25, 29) then the RSZS bit can be set to one, which may provide a lower occurrence of slips in certain applications. 128 DS26401 Octal T1/E1/J1 Framer 9.13 Fractional T1 Support (Gapped Clock Mode) The DS26401 can be programmed to output gapped clocks for selected channels in the receive and transmit paths to simplify connections into a USART or LAPD controller in Fractional T1/E1 or ISDN-PRI applications. When the gapped clock feature is enabled, a gated clock is output on the TCHCLK signal. The channel selection is controlled via the transmit gapped clock channel select registers (TGCCS1-TGCCS4). The transmit path is enabled for gapped clock mode with the TGCLKEN bit (TESCR.6). Both 56kbps and 64kbps channel formats are supported as determined by TESCR.7. When 56kbps mode is selected, the clock corresponding to the Data/Control bit in the channel is omitted (only the seven most significant bits of the channel have clocks). Register Name: Register Description: Register Address: (MSB) CH8 CH16 CH24 CH32 TGCCS1, TGCCS2, TGCCS3, TGCCS4 Transmit Gapped Clock Channel Select Registers 1CCh, 1CDh, 1CEh, 1CFh [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8] CH7 CH15 CH23 CH31 CH6 CH14 CH22 CH30 CH5 CH13 CH21 CH29 CH4 CH12 CH20 CH28 CH3 CH11 CH19 CH27 CH2 CH10 CH18 CH26 (LSB) CH1 CH9 CH17 CH25/Fbit TGCCS1 TGCCS2 TGCCS3 TGCCS4* Bits 0 to 7 / Transmit Channels 1 to 32 Gapped Clock Channel Select Bits (CH1 to CH32) 0 = no clock is present on TCHCLK during this channel time 1 = force a clock on TCHCLK during this channel time. The clock will be synchronous with TCLK if the elastic store is disabled, and synchronous with TSYSCLK if the elastic store is enabled. * Note that TGCCS4 has two functions: When 2.048MHz backplane mode is selected, this register allows the user to enable the 'gapped' clock on TCHCLK for any of the 32 possible backplane channels. When 1.544MHz backplane mode is selected, the LSB of this register determines whether or not a clock is generated on TCHCLK during the F-Bit time: TGCCS4.0 = 0, do not generate a clock during the F-Bit TGCCS4.0 = 1, generate a clock during the F-Bit In this mode, TGCCS4.1 to TGCCS4.7 should be set to 0. 129 DS26401 Octal T1/E1/J1 Framer 9.14 T1 Transmit Bit Oriented Code (BOC) Controller The DS26401 contains a BOC generator on the transmit side and a BOC detector on the receive side. The BOC function is available only in T1 mode. Bits 0 through 5 in the TBOC register contain the BOC message to be transmitted. Setting SBOC = 1 (THC2.6) causes the transmit BOC controller to immediately begin inserting the BOC sequence into the FDL bit position. The transmit BOC controller automatically provides the abort sequence. BOC messages will be transmitted as long as SBOC is set. Note that the TFPT (TCR1.6) control bit must be set to 'zero' for the BOC message to overwrite F-bit information being sampled on TSER. To Transmit a BOC 1) Write 6-bit code into the TBOC register. 2) Set SBOC bit in THC2 = 1. Register Name: Register Description: Register Address: Bit # Name Default 7 --0 TBOC Transmit BOC Register 163h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 TBOC5 0 4 TBOC4 0 3 TBOC3 0 2 TBOC2 0 1 TBOC1 0 0 TBOC0 0 Bit 0 / Transmit BOC Bit 0 (TBOC0). LSB of the Transmit BOC Code. Bit 1 / Transmit BOC Bit 1 (TBOC1) Bit 2 / Transmit BOC Bit 2 (TBOC2) Bit 3 / Transmit BOC Bit 3 (TBOC3) Bit 4 / Transmit BOC Bit 4 (TBOC4) Bit 5 / Transmit BOC Bit 5 (TBOC5). MSB of the Transmit BOC Code. Bits 6, 7 / Unused 130 DS26401 Octal T1/E1/J1 Framer 9.15 T1 Transmit FDL When enabled with TCR2.7, the transmit section will shift out into the T1 data stream, either the FDL (in the ESF framing mode) or the Fs bits (in the D4 framing mode) contained in the Transmit FDL register (TFDL). When a new value is written to the TFDL, it will be multiplexed serially (LSB first) into the proper position in the outgoing T1 data stream. After the full eight bits has been shifted out, the framer will signal the host microcontroller that the buffer is empty and that more data is needed by setting the TLS2.4 bit to a one. The INT will also toggle low if enabled via TIM2.4. The user has 2ms to update the TFDL with a new value. If the TFDL is not updated, the old value in the TFDL will be transmitted once again. Note that in this mode, no zero stuffing will be applied to the FDL data. In the D4 framing mode, the framer uses the TFDL register to insert the Fs framing pattern. To allow the device to properly insert the Fs framing pattern, the TFDL register must be programmed to 1Ch and the following bits must be programmed as shown: TCR2.7 = 0 (source Fs data from the TFDL register) TCR2.6 = 1 (allow the TFDL register to load on multiframe boundaries). Register Name: Register Description: Register Address: Bit # Name Default 7 TFDL7 0 TFDL Transmit FDL Register 162h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 TFDL6 0 5 TFDL5 0 4 TFDL4 1 3 TFDL3 1 2 TFDL2 1 1 TFDL1 0 0 TFDL0 0 Note: Also used to insert Fs framing pattern in D4 framing mode. The Transmit FDL Register (TFDL) contains the Facility Data Link (FDL) information that is to be inserted on a byte basis into the outgoing T1 data stream. The LSB is transmitted first. In D4 mode, only the lower six bits are used. Bit 0 / Transmit FDL Bit 0 (TFDL0). LSB of the Transmit FDL Code. Bit 1 / Transmit FDL Bit 1 (TFDL1) Bit 2 / Transmit FDL Bit 2 (TFDL2) Bit 3 / Transmit FDL Bit 3 (TFDL3) Bit 4 / Transmit FDL Bit 4 (TFDL4) Bit 5 / Transmit FDL Bit 5 (TFDL5) Bit 6 / Transmit FDL Bit 6 (TFDL6) Bit 7 / Transmit FDL Bit 7 (TFDL7). MSB of the Transmit FDL Code. 131 DS26401 Octal T1/E1/J1 Framer 9.16 Transmit SLC-96 Operation In a SLC-96 based transmission scheme, the standard Fs bit pattern is robbed to make room for a set of message fields. The SLC-96 multiframe is made up of six D4 superframes, hence it is 72 frames long. In the 72-frame SLC- 96 multiframe, 36 of the framing bits are the normal Ft pattern and the other 36 bits are divided into alarm, maintenance, spoiler, and concentrator bits as well as 12 bits of the normal Fs pattern. Additional SLC-96 information can be found in BellCore document TR-TSY-000008. To insert the SLC-96 message fields, the user has the option to either use the external TLINK pin or the use the onboard TFDL register. Use of the TLINK pin will require additional circuitry, and to enable this option the TCR2.7 bit should be set to one. To insert the SLC-96 message using the TFDL register, the user should configure the DS26401 as shown below: TCR2.6 (TSLC96) = 1 TCR2.7 (TFDLS) = 0 TCR3.2 (TFM) = 1 TCR1.6 (TFPT) = 0 Enable Transmit SLC-96 Source FS bits via TFDL or SLC96 formatter D4 framing Mode Do not 'pass through' TSER F-bits. The DS26401 will automatically insert the 12-bit alignment pattern in the Fs bits for the SLC96 data link frame. Data from the TSLC1-TSLC3 will be inserted into the remaining Fs bit locations of the SLC96 multiframe. The status bit TSLC96 located at TLS1.4 will set to indicate that the SLC96 data link buffer has been transmitted and that the user should write new message data into TSLC1-TSLC3. The host will have 2.5ms after the assertion of TLS1.4 to write the registers TSLC1-TSLC3. If no new data is provided in these registers, the previous values will be retransmitted. Register Name: Register Description: Register Address: TSLC1, TSLC2, TSLC3 Transmit SLC96 Data Link Registers 164h, 165h, 166h [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8] (LSB) C1 C9 M3 (MSB) C8 M2 S=1 C7 M1 S4 C6 S=0 S3 C5 S=1 S2 C4 S=0 S1 C3 C11 A2 C2 C10 A1 TSLC1 TSLC2 TSLC3 132 DS26401 Octal T1/E1/J1 Framer 9.17 Transmit HDLC Controller The HDLC controller can be mapped into a single time slot, or Sa4 to Sa8 bits (E1 Mode) or the FDL (T1 Mode). The HDLC controller has a 64-byte FIFO buffer in both the transmit and receive paths. The user can select any specific bits within the time slot(s) to assign to the HDLC controller, as well as specific Sa bits (E1 Mode). The HDLC controller performs all the necessary overhead for generating and receiving Performance Report Messages (PRM) as described in ANSI T1.403 and the messages as described in AT&T TR54016. The HDLC controller automatically generates and detects flags, generates and checks the CRC check sum, generates and detects abort sequences, stuffs and de-stuffs zeros, and byte aligns to the data stream. 133 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 NOFS 0 THC1 Transmit HDLC Control Register 1 110h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 TEOML 0 5 THR 0 4 THMS 0 3 TFS 0 2 TEOM 0 1 TZSD 0 0 TCRCD 0 Bit 0 / Transmit CRC Defeat (TCRCD). A 2-byte CRC code is automatically appended to the outbound message. This bit can be used to disable the CRC function. 0 = enable CRC generation (normal operation) 1 = disable CRC generation Bit 1 / Transmit Zero Stuffer Defeat (TZSD). The Zero Stuffer function automatically inserts a zero in the message field (between the flags) after 5 consecutive ones to prevent the emulation of a flag or abort sequence by the data pattern. The receiver automatically removes (de-stuffs) any zero after 5 ones in the message field. 0 = enable the zero stuffer (normal operation) 1 = disable the zero stuffer Bit 2 / Transmit End of Message (TEOM). Should be set to a one just before the last data byte of an HDLC packet is written into the transmit FIFO at THF. If not disabled via TCRCD, the transmitter will automatically append a 2byte CRC code to the end of the message. Bit 3 / Transmit Flag/Idle Select (TFS). This bit selects the inter-message fill character after the closing and before the opening flags (7Eh). 0 = 7Eh 1 = FFh Bit 4 / Transmit HDLC Mapping Select (THMS) 0 = Transmit HDLC assigned to channels 1 = Transmit HDLC assigned to FDL(T1 mode), Sa Bits(E1 mode) Bit 5 / Transmit HDLC Reset (THR). Will reset the transmit HDLC controller and flush the transmit FIFO. An abort followed by 7Eh or FFh flags/idle will be transmitted until a new packet is initiated by writing new data into the FIFO. Must be cleared and set again for a subsequent reset. 0 = Normal operation 1 = Reset transmit HDLC controller and flush the transmit FIFO Bit 6 / Transmit End of Message and Loop (TEOML). To loop on a message, should be set to a one just before the last data byte of an HDLC packet is written into the transmit FIFO. The message will repeat until the user clears this bit or a new message is written to the transmit FIFO. If the host clears the bit, the looping message will complete then flags will be transmitted until new message is written to the FIFO. If the host terminates the loop by writing a new message to the FIFO the loop will terminate, one or two flags will be transmitted and the new message will start. If not disabled via TCRCD, the transmitter will automatically append a 2-byte CRC code to the end of all messages. Bit 7 / Number of Flags Select (NOFS) 0 = send one flag between consecutive messages 1 = send two flags between consecutive messages 134 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 TABT 0 THC2 Transmit HDLC Control Register 2 113h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 SBOC 0 5 THCEN 0 4 THCS4 0 3 THCS3 0 2 THCS2 0 1 THCS1 0 0 THCS0 0 Bits 0 to 4 / Transmit HDLC Channel Select (THCS0 to 4). Determines which DSO channel will carry the HDLC message if enabled. Bit 5 / Transmit HDLC Controller Enable (THCEN) 0 = Transmit HDLC Controller is not enabled 1 = Transmit HDLC Controller is enabled Bit 6 / Send BOC (SBOC). Set = 1 to transmit the BOC code placed in bits 0 to 5 of the TBOC register. Bit 7 / Transmit Abort (TABT). A 0-to-1 transition will cause the FIFO contents to be dumped and one FEh abort to be sent followed by 7Eh or FFh flags/idle until a new packet is initiated by writing new data into the FIFO. Must be cleared and set again for a subsequent abort to be sent. Register Name: Register Description: Register Address: Bit # Name Default 7 TBSE8 0 THBSE Transmit HDLC Bit Suppress 111h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 TBSE7 0 5 TBSE6 0 4 TBSE5 0 3 TBSE4 0 2 TBSE3 0 1 TBSE2 0 0 TBSE1 0 Bit 0 / Transmit Bit 1 Suppress (TBSE1). LSB of the channel. Set to one to stop this bit from being used. Bit 1 / Transmit Bit 2 Suppress (TBSE2). Set to one to stop this bit from being used. Bit 2 / Transmit Bit 3 Suppress (TBSE3). Set to one to stop this bit from being used. Bit 3 / Transmit Bit 4 Suppress (TBSE4). Set to one to stop this bit from being used. Bit 4 / Transmit Bit 5 Suppress (TBSE5). Set to one to stop this bit from being used. Bit 5 / Transmit Bit 6 Suppress (TBSE6). Set to one to stop this bit from being used. Bit 6 / Transmit Bit 7 Suppress (TBSE7). Set to one to stop this bit from being used. Bit 7 / Transmit Bit 8 Suppress (TBSE8). MSB of the channel. Set to one to stop this bit from being used. 135 DS26401 Octal T1/E1/J1 Framer 9.17.1 Transmit HDLC FIFO Control Control of the transmit FIFO is accomplished via the Transmit HDLC FIFO Control (THFC). The FIFO Control register sets the watermarks for the receive FIFO. When the transmit FIFO empties below the low watermark, the TLWM bit in the appropriate HDLC status register will be set. TLWM is a real-time bit and remains set as long as the transmit FIFO's write pointer is below the watermark. If enabled, this condition can also cause an interrupt via the INT pin. Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 THFC Transmit HDLC FIFO Control Register 187h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 -- 0 1 TFLWM1 0 0 TFLWM0 0 Bit 0 to Bit 1 / Transmit HDLC FIFO Low Watermark Select (TFLWM0 to TFLWM1) TFLWM1 0 0 1 1 TFLWM0 0 1 0 1 Transmit FIFO Watermark 4 bytes 16 bytes 32 bytes 48 bytes Bits 2 to 7 / Unused. Must be set = 0 for proper operation. 136 DS26401 Octal T1/E1/J1 Framer 9.17.2 HDLC Status and Information TLS2 provides status information for the transmit HDLC controller. When a particular event has occurred (or is occurring), the appropriate bit in one of these registers will be set to a one. Some of the bits in these registers are latched and some are real time bits that are not latched. This section contains register descriptions that list which bits are latched and which are real time. With the latched bits, when an event occurs and a bit is set to a one, it will remain set until the user reads that bit. The bit will be cleared when it is read and it will not be set again until the event has occurred again. The real time bits report the current instantaneous conditions that are occurring and the history of these bits is not latched. Like the other latched status registers, the user will follow a read of the status bit with a write. The byte written to the register will inform the device which of the latched bits the user wishes to clear (the real-time bits are not affected by writing to the status register). The user will write a byte to one of these registers, with a one in the bit positions he or she wishes to clear and a zero in the bit positions he or she does not wish to clear. The HDLC status register, TLS2 has the ability to initiate a hardware interrupt via the INT output signal. Each of the events in this register can be either masked or unmasked from the interrupt pin via the receive HDLC Interrupt Mask Register (TIM2). Interrupts will force the INT signal low when the event occurs. The INT pin will be allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the interrupt to occur. Register Name: Register Description: Register Address: TRTS2 Transmit Real-Time Status Register 2 (HDLC) 1B1h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 Bit # 7 6 5 Name -- -- -- Default 0 0 0 All bits in this register are real time. 4 -- 0 3 TEMPTY 0 2 TFULL 0 1 TLWM 0 0 TNF 0 Bit 0 / Transmit FIFO Not Full Condition (TNF). Set when the transmit 64-byte FIFO has at least 1 byte available. Bit 1 / Transmit FIFO Below Low Watermark Condition (TLWM). Set when the transmit 64-byte FIFO empties beyond the low watermark as defined by the Transmit Low Watermark Bits (TLWM). Bit 2 / Transmit FIFO Full (TFULL). A real-time bit that is set high when the FIFO is full. Bit 3 / Transmit FIFO Empty (TEMPTY). A real-time bit that is set high when the FIFO is empty. Bits 4 to 7 / Unused 137 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 TLS2 Transmit Latched Status Register 2 (HDLC) 191h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 -- 0 4 TFDLE 0 3 TUDR 0 2 TMEND 0 1 TLWMS 0 0 TNFS 0 All bits in this register are latched and can create interrupts. Bit 0 / Transmit FIFO Not Full Set Condition (TNFS). Set when the transmit 64-byte FIFO has at least one empty byte available for write. Rising edge detect of TNF. Indicates change of state from full to not full. Bit 1 / Transmit FIFO Below Low Watermark Set Condition (TLWMS). Set when the transmit 64-byte FIFO empties beyond the low watermark as defined by the Transmit Low Watermark Bits (TLWM) (rising edge detect of TLWM). Bit 2 / Transmit Message End Event (TMEND). Set when the transmit HDLC controller has finished sending a message. Bit 3 / Transmit FIFO Underrun Event (TUDR). Set when the transmit FIFO empties out without having seen the TMEND bit set. An abort is automatically sent. Bit 4 / Transmit FDL Register Empty (TFDLE). Set when the TFDL register has shifted out all 8 bits. Useful if the user wants to manually use the TFDL register to send messages, instead of using the HDLC or BOC controller circuits. Bits 5 to 7 / Unused 138 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 TIM2 Transmit Interrupt Mask Register 2 1A1h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 -- 0 4 TFDLE 0 3 TUDR 0 2 TMEND 0 1 TLWMS 0 0 TNFS 0 Bit 0 / Transmit FIFO Not Full Set Condition (TNFS) 0 = interrupt masked 1 = interrupt enabled Bit 1 / Transmit FIFO Below Low Watermark Set Condition (TLWMS) 0 = interrupt masked 1 = interrupt enabled Bit 2 / Transmit Message End Event (TMEND) 0 = interrupt masked 1 = interrupt enabled Bit 3 / Transmit FIFO Underrun Event (TUDR) 0 = interrupt masked 1 = interrupt enabled Bit 4 / Transmit FDL Register Empty (TFDLE) 0 = interrupt masked 1 = interrupt enabled Bits 5 to 7 / Unused. Must be set = 0 for proper operation. 139 DS26401 Octal T1/E1/J1 Framer 9.17.3 FIFO Information The Transmit FIFO Buffer Available register indicates the number of bytes that can be written into the transmit FIFO. The count form this register informs the host as to how many bytes can be written into the transmit FIFO without overflowing the buffer. This is a real-time register. The count shall remain valid and stable during the read cycle. Register Name: Register Description: Register Address: Bit # Name Default 7 0 TFBA Transmit HDLC FIFO Buffer Available 1B3h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 TFBA6 0 5 TFBA5 0 4 TFBA4 0 3 TFBA3 0 2 TFBA2 0 1 TFBA1 0 0 TFBA0 0 Bits 0 to 6 / Transmit FIFO Bytes Available (TFBAO to TFBA6). TFBA0 is the LSB. Register Name: Register Description: Register Address: THF Transmit HDLC FIFO 1B4h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 Bit # Name Default 7 THD7 0 6 THD6 0 5 THD5 0 4 THD4 0 3 THD3 0 2 THD2 0 1 THD1 0 0 THD0 0 Bit 0 / Transmit HDLC Data Bit 0 (THD0). LSB of a HDLC packet data byte. Bit 1 / Transmit HDLC Data Bit 1 (THD1) Bit 2 / Transmit HDLC Data Bit 2 (THD2) Bit 3 / Transmit HDLC Data Bit 3 (THD3) Bit 4 / Transmit HDLC Data Bit 4 (THD4) Bit 5 / Transmit HDLC Data Bit 5 (THD5) Bit 6 / Transmit HDLC Data Bit 6 (THD6) Bit 7 / Transmit HDLC Data Bit 7 (THD7). MSB of a HDLC packet data byte. 140 DS26401 Octal T1/E1/J1 Framer 9.18 HDLC Transmit Example The HDLC status registers in the DS26401 allow for flexible software interface to meet the user's preferences. When transmitting HDLC messages, the host can chose to be interrupt driven, or to poll to desired status registers, or a combination of polling and interrupt processes may be used. An example routine for using the DS26401 HDLC receiver is given in Figure 9-1. Figure 9-1. HDLC Message Transmit Example Configure Transmit HDLC Controller (THC1,THC2,THBSE,THFC) Reset Transmit HDLC Controller (THC.5) Enable TLWM Interrupt and Verify TLWM Clear Set TEOM (THC1.2) Read TFBA N = TFBA[6..0] Push Last Byte into Tx FIFO Push Message Byte into Tx HDLC FIFO (THF) Loop N Last Byte of Message? NO TLWM Interrupt? YES NO NO YES Enable TMEND Interrupt TMEND Interrupt? YES Read TUDR Status Bit NO A A TUDR = 1 A YES No Action Required Work Another Process Disable TMEND Interrupt Prepare New Message Disable TMEND Interrupt Resend Message 141 DS26401 Octal T1/E1/J1 Framer 9.19 Programmable In-Band Loop-Code Generator The DS26401 has the ability to generate and detect a repeating bit pattern from one to eight bits or sixteen bits in length. This function is available only in T1 mode. To transmit a pattern, the user will load the pattern to be sent into the Transmit Code Definition registers (TCD1&TCD2) and select the proper length of the pattern by setting the TC0 and TC1 bits in Transmit Control Register 4 (TCR4). When generating a 1-, 2-, 4-, 8-, or 16-bit pattern both transmit code definition registers (TCD1&TCD2) must be filled with the proper code. Generation of a 3, 5, 6 and 7 bit pattern only requires TCD1 to be filled. Once this is accomplished, the pattern will be transmitted as long as the TLOOP control bit (TCR3.0) is enabled. Normally (unless the transmit formatter is programmed to not insert the Fbit position) the framer will overwrite the repeating pattern once every 193 bits to allow the F-bit position to be sent. As an example, to transmit the standard "loop-up" code for Channel Service Units (CSUs), which is a repeating pattern of ...10000100001..., set TCD1 = 80h, TC0=0, TC1=0, and TCR3.0 = 1. This register definition is repeated here for convenience. Register Name: Register Description: Register Address: TCR4 Transmit Control Register 4 186h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 Bit # Name Default 7 0 6 0 5 0 4 0 3 TRAIM 0 2 TAISM 0 1 TC1 0 0 TC0 0 Bits 0 to 1 / Transmit Code Length Definition Bits (TC0 to TC1) TC1 0 0 1 1 TC0 0 1 0 1 LENGTH SELECTED (BITS) 5 6/3 7 16/8/4/2/1 Bit 2 / Transmit AIS Mode (TAISM). Determines the pattern sent when TAIS (TCR1.1) is activated. 0 = transmit normal AIS (unframed all ones) upon activation with TCR1.1 1 = transmit AIS-CI (T1.403) upon activation with TCR1.1 Bit 3 / Transmit RAI Mode (TRAIM). Determines the pattern sent when TRAI (TCR1.0) is activated in ESF frame mode only. 0 = transmit normal RAI upon activation with TCR1.0 1 = transmit RAI-CI (T1.403) upon activation with TCR1.0 Bits 4 to 7 / Unused. Must be set = 0 for proper operation. 142 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 C7 0 TCD1 Transmit Code Definition Register 1 1ACh + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Bit 0 / Transmit Code Definition Bit 0 (C0). A Don't Care if a 5-, 6-, or 7-bit length is selected. Bit 1 / Transmit Code Definition Bit 1 (C1). A Don't Care if a 5- or 6-bit length is selected. Bit 2 / Transmit Code Definition Bit 2 (C2). A Don't Care if a 5-bit length is selected. Bit 3 / Transmit Code Definition Bit 3 (C3) Bit 4 / Transmit Code Definition Bit 4 (C4) Bit 5 / Transmit Code Definition Bit 5 (C5) Bit 6 / Transmit Code Definition Bit 6 (C6) Bit 7 / Transmit Code Definition Bit 7 (C7). First bit of the repeating pattern. Register Name: Register Description: Register Address: Bit # Name Default 7 C7 0 TCD2 Transmit Code Definition Register 2 1ADh + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Bits 0 to 7 / Transmit Code Definition Bit 0 to 7 (C0 to C7). A Don't Care if a 5-, 6-, or 7-bit length is selected. 143 DS26401 Octal T1/E1/J1 Framer 9.20 Interleaved PCM Bus Operation (IBO) In many architectures, the PCM outputs of individual framers are combined into higher speed PCM buses to simplify transport across the system backplane. The DS26401 can be configured to allow PCM data to be multiplexed into higher speed buses eliminating external hardware, saving board space and cost. The DS26401 can be configured for channel or frame interleave. The interleaved PCM bus option (IBO) supports three bus speeds. The 4.096 MHz bus speed allows two PCM data streams to share a common bus. The 8.192 MHz bus speed allows four PCM data streams to share a common bus. The 16.384 MHz bus speed allows 8 PCM data streams to share a common bus. The receive elastic stores of each transceiver must be enabled. Via the IBO register the user can configure each framer for a specific bus position. For all IBO bus configurations each framer is assigned an exclusive position in the high speed PCM bus. The 8kHz frame sync can be generated from the system backplane or from the first device on the bus. All other devices on the bus must have their frame syncs configured as inputs. Relative to this common frame sync, the devices will await their turn to drive or sample the bus according to the settings of the DA0, DA1 and DA2 bits of the TIBOC register. 9.20.1 Channel Interleave In channel interleave mode data is output to the PCM Data Out bus one channel at a time from each of the connected DS26401s until all channels of frame n from each framer has been placed on the bus. This mode can be used even when the DS26401s are operating asynchronous to each other. The elastic stores will manage slip conditions. The DS26401 provides an active-low signal (TIBO_OEB) during bus active times. TIBO_OEB can be used for bus multiplexer or tri-state buffer control. 9.20.2 Frame Interleave In frame interleave mode data is output to the PCM Data Out bus one frame at a time from each of the framers. This mode is used only when all connected DS26401s are operating in a synchronous fashion (all inbound T1 or E1 lines are synchronous) and are synchronous with the system clock (system clock derived from T1 or E1 line). In this mode, slip conditions are not allowed. 144 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 TIBOC Transmit Interleave Bus Operation Control Register 188h 6 IBS1 0 5 IBS0 0 4 IBOSEL 0 3 IBOEN 0 2 DA2 0 1 DA1 0 0 DA0 0 Bits 0 to 2 / Device Assignment Bits (DA0 to DA2) DA2 0 0 0 0 1 1 1 1 DA1 0 0 1 1 0 0 1 1 DA0 0 1 0 1 0 1 0 1 Device Position 1st Device on bus 2nd Device on bus 3rd Device on bus 4th Device on bus 5th Device on bus 6th Device on bus 7th Device on bus 8th Device on bus Bit 3 / Interleave Bus Operation Enable (IBOEN) 0 = Interleave Bus Operation disabled. 1 = Interleave Bus Operation enabled. Bit 4 / Interleave Bus Operation Select (IBOSEL). This bit selects channel or frame interleave mode. 0 = Channel Interleave 1 = Frame Interleave Bits 5 to 6 / IBO Bus Size bit 1 (IBS0 to IBS1). Indicates how many devices on the bus. IBS1 0 0 1 1 IBS0 0 1 0 1 Bus Size 2 Devices on bus 4 Devices on bus 8 Devices on bus Reserved for future use Bit 7 / Unused. Must be set = 0 for proper operation. 145 DS26401 Octal T1/E1/J1 Framer 9.21 Interfacing the T1 Tx Formatter to the BERT Data from the BERT can be inserted into the DS26401 transmit formatter data stream by using the registers described below. Either framed or unframed format can be transmitted, controlled by the TBFUS bit in the TBICR. Any signal DS0, combination of DS0s, or the entire bandwidth can be replaced with the BERT data as controlled by the TBCS registers. Note that one BERT resource is shared between all 8 framers. Therefore, the TBEN bit should be set for only one framer at a time. If multiple framers have the TBEN bit set, the lower number framer will be assigned the resource. Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 TBICR Transmit BERT Interface Control Register 18Ah + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 TBDC 0 1 TBFUS 0 0 TBEN 0 Bit 0 / Transmit BERT Enable (TBEN) 0 = Transmit BERT is not assigned to this framer. 1 = Transmit BERT is assigned to this framer. Bit 1 / Transmit BERT Framed/Unframed Select (TBFUS) 0 = The framer will not provide data from the F-bit position (framed) 1 = The framer will clock data from the F-bit position (unframed) Bit 2 / Transmit BERT Direction Control (TBDC) 0 = Transmit Path: The BERT transmits toward the network via the TPOS and TNEG pins. 1 = Backplane: The BERT transmits toward the system backplane via the RSER pin. Bits 3 to 7 / Unused. Must be set = 0 for proper operation. Register Name: Register Description: Register Address: TBCS1, TBCS2, TBCS3 Transmit BERT Channel Select Registers 0D4h, 0D5h, 0D6h [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8] Setting any of the CH1 through CH24 bits in the TBCS1 through TBCS3 registers will map data from those channels to the on-board BERT. TBEN must be set to one for these registers to function. Multiple, or all channels may be selected simultaneously. These registers affect the transmit-side framer only. (MSB) CH8 CH16 CH24 (LSB) CH1 CH9 CH17 CH7 CH15 CH23 CH6 CH14 CH22 CH5 CH13 CH21 CH4 CH12 CH20 CH3 CH11 CH19 CH2 CH10 CH18 TBCS1 TBCS2 TBCS3 146 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: TBBS Transmit BERT Bit Suppress Register 18Bh Bit # Name Default 7 BSE8 0 6 BSE7 0 5 BSE6 0 4 BSE5 0 3 BSE4 0 2 BSE3 0 1 BSE2 0 0 BSE1 0 Bit 0 / Transmit Channel Bit 1 Suppress (BSE1). LSB of the channel. Set to one to stop this bit from being used. Bit 1 / Transmit Channel Bit 2 Suppress (BSE2). Set to one to stop this bit from being used. Bit 2 / Transmit Channel Bit 3 Suppress (BSE3). Set to one to stop this bit from being used. Bit 3 / Transmit Channel Bit 4 Suppress (BSE4). Set to one to stop this bit from being used. Bit 4 / Transmit Channel Bit 5 Suppress (BSE5). Set to one to stop this bit from being used. Bit 5 / Transmit Channel Bit 6 Suppress (BSE6). Set to one to stop this bit from being used. Bit 6 / Transmit Channel Bit 7 Suppress (BSE7). Set to one to stop this bit from being used. Bit 7 / Transmit Channel Bit 8 Suppress (BSE8). MSB of the channel. Set to one to stop this bit from being used. 147 DS26401 Octal T1/E1/J1 Framer 9.22 T1 Transmit Synchronizer When enabled, the DS26401 transmitter has the ability to identify the D4 or ESF frame boundary within the incoming NRZ data stream at TSER. The TFM (TCR3.2) control bit determines whether the transmit synchronizer searches for the D4 or ESF multiframe. Additional control signals for the transmit synchronizer are located in the TSYNCC register. The Transmit Latched Status 3 (TLS3) register provides a latched status bit (LOFD) to indicate that a Loss-of-Frame synchronization has occurred, and a real-time bit (LOF) which is set high when the synchronizer is searching for frame/multiframe alignment. The LOFD bit can be enabled to cause an interrupt condition on INT. Note that when the transmit synchronizer is used, the TSYNC signal should be set as an output (TSIO = 1) and the recovered frame sync pulse will be output on this signal. The recovered multiframe sync pulse will be output if enabled with TIOCR.0 (TSM = 1). The transmit synchronizer cannot be used while the transmit elastic store is enabled. Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 TSYNCC Transmit Synchronizer Control Register 18Eh + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 TSEN 0 1 SYNCE 0 0 RESYNC 0 Bit 0 / Resynchronize (RESYNC) When toggled from low to high, a resynchronization of the transmit side framer is initiated. Must be cleared and set again for a subsequent resync. Bit 1 / Sync Enable (SYNCE) 0 = auto resync enabled 1 = auto resync disabled Bit 2 / Transmit Synchronizer Enable (TSEN) 0 = Transmit Synchronizer Disabled 1 = Transmit Synchronizer Enabled Bits 3 to 7 / Unused. Must be set = 0 for proper operation. 148 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 TLS3 Transmit Latched Status Register 3 (Synchronizer) 192h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 -- 0 1 LOF 0 0 LOFD 0 Bit 0 / Loss Of Frame Synchronization Detect (LOFD). This latched bit is set when the transmit synchronizer is searching for the sync pattern in the incoming data stream. Bit 1 / Loss of Frame (LOF). A real-time bit that indicates that the transmit synchronizer is searching for the sync pattern in the incoming data stream. Bits 2 to 7 / Unused Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 TIM3 Transmit Interrupt Mask Register 3 (Synchronizer) 1A2h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 -- 0 1 -- 0 0 LOFD 0 Bit 0 / Loss Of Frame Synchronization Detect (LOFD) 0 = Interrupt Masked 1 = Interrupt Enabled Bits 1 to 7 / Unused. Must be set = 0 for proper operation. 149 DS26401 Octal T1/E1/J1 Framer 10. E1 RECEIVER 10.1 E1 Receiver Register Map ADDRESS 000 001 002 003 004 005 006 007 008 009 00A 00B 00C 00D 00E 00F 010 011 012 013 014 015 016 017 018 019 01A 01B 01C 01D 01E 01F 020 021 022 023 024 025 026 027 028 029 02A 02B 02C 02D 02E 02F 030 031 032 033 034 035 036 037 TYPE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- R/W R/W R/W R/W -- -- -- -- -- -- -- -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W FUNCTION Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Rx HDLC Control Rx HDLC Bit Suppress Rx DS0 Monitor Select Rx Signaling Control Unused Unused Unused Unused Unused Unused Unused Unused Rx Test Register 1 Rx Test Register 2 Rx Test Register 3 Rx Test Register 4 Rx Idle Definition 1 Rx Idle Definition 2 Rx Idle Definition 3 Rx Idle Definition 4 Rx Idle Definition 5 Rx Idle Definition 6 Rx Idle Definition 7 Rx Idle Definition 8 Rx Idle Definition 9 Rx Idle Definition 10 Rx Idle Definition 11 Rx Idle Definition 12 Rx Idle Definition 13 Rx Idle Definition 14 Rx Idle Definition 15 Rx Idle Definition 16 Rx Idle Definition 17 Rx Idle Definition 18 Rx Idle Definition 19 Rx Idle Definition 20 Rx Idle Definition 21 Rx Idle Definition 22 Rx Idle Definition 23 Rx Idle Definition 24 NAME -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- RHC RHBSE RDS0SEL RSIGC -- -- -- -- -- -- -- -- RTEST1 RTEST2 RTEST3 RTEST4 RIDR1 RIDR2 RIDR3 RIDR4 RIDR5 RIDR6 RIDR7 RIDR8 RIDR9 RIDR10 RIDR11 RIDR12 RIDR13 RIDR14 RIDR15 RIDR16 RIDR17 RIDR18 RIDR19 RIDR20 RIDR21 RIDR22 RIDR23 RIDR24 PAGE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 200 200 181 184 -- -- -- -- -- -- -- -- -- -- -- -- 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 150 DS26401 Octal T1/E1/J1 Framer ADDRESS 038 039 03A 03B 03C 03D 03E 03F 040 041 042 043 044 045 046 047 048 049 04A 04B 04C 04D 04E 04F 050 051 052 053 054 055 056 057 058 059 05A 05B 05C 05D 05E 05F 060 061 062 063 064 065 066 067 068 069 06A 06B 06C 06D 06E 06F 070 071 072 073 074 TYPE R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R R R R R R R R R R R R R R R R R -- -- -- -- -- -- -- -- R -- R -- R R R R R R R R R R -- -- -- -- -- -- -- FUNCTION Rx Idle Definition 25 Rx Idle Definition 26 Rx Idle Definition 27 Rx Idle Definition 28 Rx Idle Definition 29 Rx Idle Definition 30 Rx Idle Definition 31 Rx Idle Definition 32 Rx Signaling 1 Rx Signaling 2 Rx Signaling 3 Rx Signaling 4 Rx Signaling 5 Rx Signaling 6 Rx Signaling 7 Rx Signaling 8 Rx Signaling 9 Rx Signaling 10 Rx Signaling 11 Rx Signaling 12 Rx Signaling 13 Rx Signaling 14 Rx Signaling 15 Rx Signaling 16 Rx Line-Code Violation Counter 1 Rx Line-Code Violation Counter 2 Rx Path-Code Violation Counter 1 Rx Path-Code Violation Counter 2 Rx Frames Out-of-Sync Counter 1 Rx Frames Out-of-Sync Counter 2 Receive E-Bit Counter 1 Receive E-Bit Counter 2 Unused Unused Unused Unused Unused Unused Unused Unused Rx DS0 Monitor Unused Receive Real-Time Status 7 Unused Receive Align Frame Receive Non-Align Frame Receive Si Bits for Align Frame Receive Si Bits for Non-Align Frame Receive Remote Alarm Bits Receive Sa4 Bits Receive Sa5 Bits Receive Sa6 Bits Receive Sa7 Bits Receive Sa8 Bits Unused Unused Unused Unused Unused Unused Unused NAME RIDR25 RIDR26 RIDR27 RIDR28 RIDR29 RIDR30 RIDR31 RIDR32 RS1 RS2 RS3 RS4 RS5 RS6 RS7 RS8 RS9 RS10 RS11 RS12 RS13 RS14 RS15 RS16 LCVCR1 LCVCR2 PCVCR1 PCVCR2 FOSCR1 FOSCR2 EBCR1 EBCR2 -- -- -- -- -- -- -- -- RDS0M -- RRTS7 -- RAF RNAF RSiAF RSiNAF RRA RSa4 RSa5 RSa6 RSa7 RSa8 -- -- -- -- -- -- -- PAGE 76 76 76 76 76 76 76 76 185 185 185 185 185 185 185 185 185 185 185 185 185 185 185 185 66 66 67 67 68 68 180 180 -- -- -- -- -- -- -- -- 181 -- -- -- 194 195 195 196 196 197 197 198 198 199 -- -- -- -- -- -- -- 151 DS26401 Octal T1/E1/J1 Framer ADDRESS 075 076 077 078 079 07A 07B 07C 07D 07E 07F 080 081 082 083 084 085 086 087 088 089 08A 08B 08C 08D 08E 08F 090 091 092 093 094 095 096 097 098 099 09A 09B 09C 09D 09E 09F 0A0 0A1 0A2 0A3 0A4 0A5 0A6 0A7 0A8 0A9 0AA 0AB 0AC 0AD 0AE 0AF 0B0 0B1 TYPE -- -- -- -- -- -- -- -- -- -- -- R/W R/W R/W R/W R/W R/W R/W R/W R/W -- R/W R/W -- -- R/W R/W R/W R/W R/W R/W R/W -- -- -- R/W R/W R/W R/W -- -- -- R/W R/W R/W R/W R/W R/W -- -- -- R/W R/W R/W R/W -- -- -- -- R -- FUNCTION Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Rx Master Mode Rx Control 1 Rx Control 2 Rx Control 3 Rx I/O Configuration Rx Elastic Store Control Rx Error Count Configuration Rx HDLC FIFO Control Rx Interleave Bus Op Control Unused Rx BERT Interface Control Rx BERT Bit Suppress Enable Unused Unused Rx Test Register 5 Rx Test Register 6 Rx Latched Status 1 Rx Latched Status 2 Rx Latched Status 3 Rx Latched Status 4 Rx Latched Status 5 (HDLC) Unused Unused Unused Rx Signaling Change-of-State Status 1 Rx Signaling Change-of-State Status 2 Rx Signaling Change-of-State Status 3 Rx Signaling Change-of-State Status 4 Unused Unused Unused Rx Interrupt Information Reg Rx Interrupt Mask Reg 1 Rx Interrupt Mask Reg 2 Rx Interrupt Mask Reg 3 Rx Interrupt Mask Reg 4 Rx Interrupt Mask Reg 5 (HDLC) Unused Unused Unused Rx Signaling Change-of-State Enable 1 Rx Signaling Change-of-State Enable 2 Rx Signaling Change-of-State Enable 3 Rx Signaling Change-of-State Enable 4 Unused Unused Unused Unused Rx Real-Time Status 1 Unused NAME -- -- -- -- -- -- -- -- -- -- -- RMMR RCR1 RCR2 RCR3 RIOCR RESCR ERCNT RHFC RIBOC -- RBICR RBBS -- -- RTEST5 RTEST6 RLS1 RLS2 RLS3 RLS4 RLS5 -- -- -- RSS1 RSS2 RSS3 RSS4 -- -- -- RIIR RIM1 RIM2 RIM3 RIM4 RIM5 -- -- -- RSCSE1 RSCSE2 RSCSE3 RSCSE4 -- -- -- -- RRTS1 -- PAGE -- -- -- -- -- -- -- -- -- -- -- 156 158 159 160 161 190 176 201 209 -- 210 211 -- -- 54 56 57 59 97 -- -- -- 74 74 74 74 -- -- -- 157 167 169 171 174 206 -- -- -- 186 186 186 186 -- -- -- -- 165 -- 152 DS26401 Octal T1/E1/J1 Framer ADDRESS 0B2 0B3 0B4 0B5 0B6 0B7 0B8 0B9 0BA 0BB 0BC 0BD 0BE 0BF 0C0 0C1 0C2 0C3 0C4 0C5 0C6 0C7 0C8 0C9 0CA 0CB 0CC 0CD 0CE 0CF 0D0 0D1 0D2 0D3 0D4 0D5 0D6 0D7 0D8 0D9 0DA 0DB 0DC 0DD 0DE 0DF 0E0 0E1 0E2 0E3 0E4 0E5 0E6 0E7 0E8 0E9 0EA 0EB 0EC 0ED 0EE TYPE R -- R R R -- -- -- -- -- -- -- -- -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- FUNCTION Rx Real-Time Status 3 Unused Rx Real-Time Status 5 (HDLC) Rx HDLC Packet Bytes Available Rx HDLC FIFO Unused Unused Unused Unused Unused Unused Unused Unused Unused Rx Blank Channel Select 1 Rx Blank Channel Select 2 Rx Blank Channel Select 3 Rx Blank Channel Select 4 Rx Channel Blocking 1 Rx Channel Blocking 2 Rx Channel Blocking 3 Rx Channel Blocking 4 Rx Signaling Insertion 1 Rx Signaling Insertion 2 Rx Signaling Insertion 3 Rx Signaling Insertion 4 Rx Gapped Clock Channel Select 1 Rx Gapped Clock Channel Select 2 Rx Gapped Clock Channel Select 3 Rx Gapped Clock Channel Select 4 Rx Channel Idle Code Enable 1 Rx Channel Idle Code Enable 2 Rx Channel Idle Code Enable 3 Rx Channel Idle Code Enable 4 Rx BERT Channel Select 1 Rx BERT Channel Select 2 Rx BERT Channel Select 3 Rx BERT Channel Select 4 Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused NAME RRTS3 -- RRTS5 RHPBA RHF -- -- -- -- -- -- -- -- -- RBCS1 RBCS2 RBCS3 RBCS4 RCBR1 RCBR2 RCBR3 RCBR4 RSI1 RSI2 RSI3 RSI4 RGCCS1 RGCCS2 RGCCS3 RGCCS4 RCICE1 RCICE2 RCICE3 RCICE4 RBCS1 RBCS2 RBCS3 RBCS4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PAGE 169 -- 204 202 203 -- -- -- -- -- -- -- -- -- 191 191 191 191 188 188 188 188 186 186 186 186 193 193 193 193 187 187 187 187 191 191 191 191 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 153 DS26401 Octal T1/E1/J1 Framer ADDRESS 0EF 0F0 0F1 0F2 0F3 0F4 0F5 0F6 0F7 0F8 0F9 0FA 0FB 0FC 0FD 0FE 0FF TYPE -- -- -- -- -- -- -- -- -- -- -- -- FUNCTION Unused Used by Global Functions Used by Global Functions Unused Unused Unused Unused Unused Unused Used by Global Functions Used by Global Functions Used by Global Functions Unused Unused Unused Unused Unused NAME -- -- -- -- -- -- -- -- -- -- -- -- PAGE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Note : The register addresses are 9-bits wide, but are shown here in hexadecimal. Addresses with the MSB clear (0xxH) are used for the DS26401 receiver; addresses with the MSB set (1xxH) are used for the DS26401 transmitter. 154 DS26401 Octal T1/E1/J1 Framer 10.2 E1 Receive Framer Description and Operation Eight fully independent DS1/E1 framers are included within the DS26401. The framers are designed to interface seamlessly to the line side via an external LIU. Each framer can be individually programmed to accept AMI, HDB3 (E1), B8ZS (T1), or NRZ data. In E1 mode each framer supports FAS, CRC-4, and CAS frame formats, and detects/reports common alarms such as AIS, RAI, LOS, and LOF. Performance monitor counters are maintains for each port which report bipolar/line code violations, CRC-4 errors, FAS errors, and E-bits. Each framer has an HDLC controller which can be mapped into a single time slot, or Sa4 to Sa8 bits (E1 Mode) or the FDL (T1 Mode) and includes 64 byte FIFO buffers in both the transmit and receive paths. Host interface is simplified with status registers optimized for either interrupt driven or polled environments. In many cases, status bits are reported both real-time and latched on change-of-state with separate bits for each state change. Most latched bits can be mapped to generate an external interrupt on the INT pin. Interface to the system backplane is simplified with flexible, 2 frame elastic-store buffers. An interleaved backplane option is also provided that supports 4.096, 8.192, or 16.384 MHz operation. Additional details concerning the operation of the E1 framer are included within the register descriptions within this section. 155 DS26401 Octal T1/E1/J1 Framer 10.3 Receive Master Mode Register The Receive Master Mode Register (RMMR) controls the initialization of the receive side framer. The FRM_EN bit may be left `low' if the framer for that particular port is not going to be used, putting the circuit in a low-power (sleep) state. Register Name: Register Description: Register Address: Bit # Name Default 7 FRM_EN 0 RMMR Receive Master Mode Register 080h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 INIT_DONE 0 5 -- 0 4 -- 0 3 -- 0 2 -- 0 1 SFTRST 0 0 T1/E1 0 Bit 0 / Receiver T1/E1 Mode Select (T1/E1). Sets operating mode for receiver only! This bit must be set to the desired state before writing INIT_DONE. 0 = T1 operation 1 = E1 operation Bit 1 / Soft Reset (SFTRST). Level sensitive processor reset. Should be taken high then low to reset and initialize the internal processor. 0 = Normal operation 1 = Hold the internal RISC in reset. This bit only affects the receive side processor. Bits 2 to 5 / Unused. Must be set = 0 for proper operation. Bit 6 / Initialization Done (INIT_DONE). The host (user) must set this bit once he/she has written the configuration registers. The host is required to write or clear all RAM based registers (addresses 00H to 7FH) prior to setting this bit. Once INIT_DONE is set, the internal processor will check the FRM_EN bit. If enabled, the internal processor continues executing based on the initial configuration. Bit 7 / Framer Enable (FRM_EN). This bit must be written with the desired value prior to setting INIT_DONE. 0 = Framer disabled - held in low power state 1 = Framer enabled - all features active 156 DS26401 Octal T1/E1/J1 Framer 10.4 Interrupt Information Registers The Interrupt Information Registers provide an indication of which DS26401 Status Registers are generating an interrupt. When an interrupt occurs, the host can read RIIR to quickly identify which of the 6 E1 receive status registers are causing the interrupt. The Interrupt Information Register bits will clear once the appropriate interrupt has been serviced and cleared, as long as no other interrupt condition is present in the associated status register. Status bits that have been masked via the Receive Interrupt Mask (RIMx) registers, will also be masked from the IIR registers. Register Name: Register Description: Register Address: Bit # Name Default 7 0 RIIR Receive Interrupt Information Register 09Fh + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 0 5 RLS6 0 4 RLS5 0 3 RLS4 0 2 RLS3 0 1 RLS2 0 0 RLS1 0 157 DS26401 Octal T1/E1/J1 Framer 10.5 E1 Receive Control Registers Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 RCR1 Receive Control Register 1 081h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 RHDB3 0 5 RSIGM 0 4 RG802 0 3 RCRC4 0 2 FRC 0 1 SYNCE 0 0 RESYNC 0 Bit 0 / Resynchronize (RESYNC) When toggled from low to high, a resynchronization of the receive-side framer is initiated. Must be cleared and set again for a subsequent resync. Bit 1 / Sync Enable (SYNCE) 0 = auto resync enabled 1 = auto resync disabled Bit 2 / Frame Resync Criteria (FRC) 0 = resync if FAS received in error 3 consecutive times 1 = resync if FAS or bit 2 of non-FAS is received in error 3 consecutive times Bit 3 / Receive CRC4 Enable (RCRC4) 0 = CRC4 disabled 1 = CRC4 enabled Bit 4 / Receive G.802 Enable (RG802) 0 = do not force RCHBLK high during bit 1 of time slot 26 1 = force RCHBLK high during bit 1 of time slot 26 Bit 5 / Receive Signaling Mode Select (RSIGM) 0 = CAS signaling mode 1 = CCS signaling mode Bit 6 / Receive HDB3 Enable (RHDB3) 0 = HDB3 disabled 1 = HDB3 enabled Bit 7 / Unused. Must be set = 0 for proper operation. 158 DS26401 Octal T1/E1/J1 Framer Table 10-1. E1 Sync/Resync Criteria FRAME OR MULTIFRAME LEVEL SYNC CRITERIA RESYNC CRITERIA Three consecutive incorrect FAS received Alternate: (RCR1.2 = 1) The above criteria is met or three consecutive incorrect bit 2 of non-FAS received 915 or more CRC4 code words out of 1000 received in error Two consecutive MF alignment words received in error or for a period of 1 multiframe, all the bits in time slot 16 are zero. Alternate: (RSIGC.4 = 1) The above criteria is met or 1 multiframe is received with all bits in time slot 16 set to 0. G.706 4.1.1 and 4.1.2 ITU SPEC. FAS FAS present in frame N and N + 2, and FAS not present in frame N + 1 CRC4 Two valid MF alignment words found within 8 ms Valid MF alignment word found. G.706 4.2 and 4.3.2 CAS Alternate: (RSIGC.4 = 1) Valid MF alignment word found and previous time slot 16 contains code other than all zeros. G.732 5.2 Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 RCR2 Receive Control Register 2 082h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 -- 0 1 -- 0 0 RLOSA 0 Bit 0 / Receive Loss of Signal Alternate Criteria (RLOSA). Defines the criteria for an LOS condition. 0 = LOS declared upon 255 consecutive zeros (125ms) 1 = LOS declared upon 2048 consecutive zeros (1ms) Bits 1 to 7/ Unused. Must be set = 0 for proper operation. 159 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 IDF 0 RCR3 Receive Control Register 3 083h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 RSERC 0 4 -- 0 3 -- 0 2 RLB 0 1 PLB 0 0 FLB 0 Bit 0 / Framer Loopback (FLB) 0 = loopback disabled 1 = loopback enabled This loopback is useful in testing and debugging applications. In FLB, the DS26401 will loop data from the transmit side back to the receive side. When FLB is enabled, the following will occur: 1) (T1 mode) an unframed all one's code will be transmitted at TPOS and TNEG (E1 mode) normal data will be transmitted at TPOS and TNEG 2) Data at RPOS and RNEG will be ignored 3) All receive side signals will take on timing synchronous with TCLK instead of RCLK. Please note that it is not acceptable to have RCLK tied to TCLK during this loopback because this will cause an unstable condition. Bit 1 / Payload Loopback (PLB) 0 = loopback disabled 1 = loopback enabled When PLB is enabled, the following will occur: 1) 2) 3) 4) Data will be transmitted from the TPOS and TNEG pins synchronous with RCLK instead of TCLK All of the receive side signals will continue to operate normally The TCHCLK and TCHBLK signals are forced low Data at the TSER pin is ignored Normally, this loopback is only enabled when ESF framing is being performed but can be enabled also in D4 framing applications. In a PLB situation, the DS26401 will loop the 192 bits of payload data (with BPVs corrected) from the receive section back to the transmit section. The FPS framing pattern, CRC6 calculation, and the FDL bits are not looped back, they are reinserted by the DS26401. Bit 2 / Remote Loopback (RLB) 0 = loopback disabled 1 = loopback enabled In this loopback, data input via the RPOS and RNEG pins will be transmitted back to the TPOS and TNEG pins. Data will continue to pass through the receive side framer of the DS26401 as it would normally and the data from the transmit side formatter will be ignored. Bits 3, 4, 6 / Unused. Must be set = 0 for proper operation. Bit 5 / RSER Control (RSERC) 0 = allow RSER to output data as received under all conditions (normal operation) 1 = force RSER to one under loss of frame alignment conditions Bit 7 / Input Data Format (IDF) 0 = Bipolar data is expected at RPOS and RNEG (either AMI or B8ZS) 1 = NRZ data is expected at RPOS. The BPV counter will be disabled and RNEG will be ignored by the DS26401. 160 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 RCLKINV 0 RIOCR Receive I/O Configuration Register 084h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 RSYNCINV 0 5 H100EN 0 4 RSCLKM 0 3 -- 0 2 RSIO 0 1 RSMS2 0 0 RSMS1 0 Bit 0 / RSYNC Mode Select 1 (RSMS1). Selects frame or multiframe pulse when RSYNC pin is in output mode. In input mode (elastic store must be enabled) multiframe mode is only useful when receive signaling reinsertion is enabled. 0 = frame mode 1 = multiframe mode Bit 1 / RSYNC Mode Select 2 (RSMS2) T1: RSYNC pin must be programmed in the output frame mode 0 = do not pulse double wide in signaling frames 1 = do pulse double wide in signaling frames E1: RSYNC pin must be programmed in the output multiframe mode 0 = RSYNC outputs CAS multiframe boundaries 1 = RSYNC outputs CRC4 multiframe boundaries Bit 2 / RSYNC I/O Select (RSIO). (Note: This bit must be set to zero when elastic store is disabled.) 0 = RSYNC is an output 1 = RSYNC is an input (only valid if elastic store enabled) Bit 3 / Unused. Must be set = 0 for proper operation. Bit 4 / RSYSCLK Mode Select (RSCLKM) 0 = if RSYSCLK is 1.544MHz 1 = if RSYSCLK is 2.048MHz or IBO enabled Bit 5 / H.100 SYNC Mode (H100EN). See Section 10.6. 0 = Normal operation 1 = RSYNC and TSSYNC shifted Bit 6 / RSYNC Invert (RSYNCINV) 0 = No inversion 1 = Invert RSYNC as either input or output Bit 7 / RCLK Invert (RCLKINV) 0 = No inversion 1 = Invert RCLK input 161 DS26401 Octal T1/E1/J1 Framer 10.6 H.100 (CT Bus) Compatibility The H.100 (or CT Bus) is a synchronous, bit-serial, TDM transport bus operating at 8.192MHz. The H.100 standard also allows compatibility modes to operate at 2.048MHz, 4.096MHz, or 8.192MHz. The control bit H100EN (RIOCR.5), when combined with RSYNCINV and TSSYNCINV allows the DS26401 to accept the CT-Bus compatible frame sync signal (/CT_FRAME) at the RSYNC and TSSYNC inputs. The following rules apply to the H100EN control bit: 1) The H100EN bit controls the sampling point for the RSYNC (input mode) and TSSYNC only (the RSYNC output and other sync signals are not affected). 2) The H100EN bit would always be used in conjunction with the receive and transmit elastic store buffers. 3) The H100EN bit would typically be used with 8.192MHz IBO mode (Section 8.21), but could also be used with 4.096MHz IBO mode or 2.048MHz backplane operation. 4) The H100EN bit in RIOCR controls both RSYNC and TSSYNC (i.e., there is no separate control bit for the TSSYNC). 5) The H100EN bit does not invert the expected signal, RSYNCINV (RIOCR) and TSSYNCINV (TIOCR) must be set `high' to invert the inbound sync signals. Figure 10-1. RSYNC Input in H.100 (CT Bus) Mode RSYNC1 RSYNC2 RSYSCLK RSER Bit 8 Bit 1 Bit 2 tbc3 NOTE 1: RSYNC INPUT MODE IN NORMAL OPERATION. NOTE 2: RSYNC INPUT MODE, H100EN = 1 and RSYNCINV = 1. NOTE 3: tbc (BIT-CELL TIME) = 122ns (typ). tbc = 244ns or 488ns ALSO ACCEPTABLE. 162 DS26401 Octal T1/E1/J1 Framer Figure 10-2. TSSYNC Input in H.100 (CT Bus) Mode TSSYNC1 TSSYNC2 TSYSCLK TSER Bit 8 Bit 1 Bit 2 tbc3 NOTE 1: TSSYNC IN NORMAL OPERATION. NOTE 2: TSSYNC WITH H100EN = 1 and TSSYNCINV = 1. NOTE 3: tbc (BIT-CELL TIME) = 122ns (typ). tbc = 244ns or 488ns ALSO ACCEPTABLE. 163 DS26401 Octal T1/E1/J1 Framer 10.7 E1 Receive Status and Information When a particular event has occurred (or is occurring), the appropriate bit in one of these registers will be set to a one. Status bits may operate in either a latched or real-time fashion. Some latched bits may be enabled to generate a hardware interrupt via the INT signal. Real-Time Bits Some status bits operate in a real-time fashion. These bits are read-only and indicate the present state of an alarm or a condition. Real-time bits remain stable and valid during the host read operation. The current value of the internal status signals can be read at any time from the real time status registers without changing any the latched status register bits Latched Bits When an event or an alarm occurs and a latched bit is set to a one, it will remain set until cleared by the user. These bits typically respond on a change-of-state for an alarm, condition, or event; and operate in a read-then-write fashion. The user should read the value of the desired status bit, and then write a 1 to that particular bit location in order to clear the latched value (write a 0 to locations not to be cleared). Once the bit is cleared, it will not be set again until the event has occurred again. Mask Bits Some of the alarms and events can be either masked or unmasked from the interrupt pin via the Interrupt Mask Registers (RIMx). When unmasked, the INT signal will be forced low when the enabled event or condition occurs. The INT pin will be allowed to return high (if no other unmasked interrupts are present) when the user reads then clears (with a write) the alarm bit that caused the interrupt to occur. Note that the latched status bit and the INT pin will clear even if the alarm is still present. Note that some conditions may have multiple status indications. For example, Receive Loss of Frame (RLOF) provides the following indications: Real-time indication that the receiver is not synchronized with incoming data stream. Read-only bit that remains high as long as the condition is present. Latched indication that the receiver has loss synchronization since the bit was last cleared. Bit will clear when written by the user, even if the condition is still present (rising edge detect of RRTS1.0). Latched indication that the receiver has reacquired synchronization since the bit was last cleared. Bit will clear when written by the user, even if the condition is still present (falling edge detect of RRTS1.0). RRTS1.0 (RLOF) RLS1.0 (RLOFD) RLS1.4 (RLOFC) 164 DS26401 Octal T1/E1/J1 Framer Table 10-2. E1 Alarm Criteria ALARM RLOF SET CRITERIA An RLOF condition exist on power up prior to initial synchronization, when a resync criteria has been met, or when a manual resync has been initiated via RCR1.0 255 or 2048 consecutive zeros received as determined by RCR2.0 Bit 3 of non-align frame set to one for three consecutive occasions In 255-bit times, at least 32 ones are received Bit 3 of non-align frame set to zero for three consecutive occasions More than two zeros in two frames (512 bits) G.775/G.962 CLEAR CRITERIA ITU SPEC. RLOS RRAI O.162 RAIS Fewer than three zeros in two frames (512 bits) O.162 RDMA Bit 6 of time slot 16 in frame 0 has been set for two consecutive multiframes V52LNK 2 out of 3 Sa7 bits are zero G.965 Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 RRTS1 Receive Real-Time Status Register 1 0B0h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 -- 0 4 -- 0 3 RRAI 0 2 RAIS 0 1 RLOS 0 0 RLOF 0 All bits in this register are real-time (not latched). Bit 0 / Receive Loss of Frame Condition (RLOF). Set when the DS26401 is not synchronized to the received data stream. Bit 1 / Receive Loss of Signal Condition (RLOS). Set when 255 (or 2048 if RCR2.0 = 1) consecutive zeros have been detected at RPOS and RNEG. Bit 2 / Receive Alarm Indication Signal Condition (RAIS). Set when an unframed all one's code is received at RPOS and RNEG. Bit 3 / Receive Remote Alarm Indication Condition (RRAI). Set when a remote alarm is received at RPOS and RNEG. Bits 4 to 7 / Unused 165 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 RRAIC 0 RLS1 Receive Latched Status Register 1 090h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 RAISC 0 5 RLOSC 0 4 RLOFC 0 3 RRAID 0 2 RAISD 0 1 RLOSD 0 0 RLOFD 0 All bits in this register are latched and can create interrupts. Bit 0 / Receive Loss of Frame Condition Detect (RLOFD). Change of state indication that the DS26401 has lost synchronized to the received data stream (rising edge detect of RLOF). Bit 1 / Receive Loss of Signal Condition Detect (RLOSD). Change of state indication. Set when 255 (or 2048 if RCR2.0 = 1) consecutive zeros have been detected at RPOS and RNEG (rising edge detect of RLOS). Bit 2 / Receive AIS Condition Detect (RAISD). Change of state indication. Set when an unframed all one's code is received at RPOS and RNEG (rising edge detect of RAIS). Bit 3 / Receive Remote Alarm Condition Detect (RRAID). Change of state indication. Set when a remote alarm is received at RPOS and RNEG (rising edge detect of RRAI). Bit 4 / Receive Loss of Frame Condition Clear (RLOFC). Change of state indication. Set when an RLOF condition has cleared (falling edge detect of RLOF). Bit 5 / Receive Loss of Signal Condition Clear (RLOSC). Change of state indication. Set when an RLOS condition has cleared (falling edge detect of RLOS). Bit 6 / Receive AIS Condition Clear (RAISC). Change of state indication. Set when a RAIS condition has cleared (falling edge detect of RAIS). Bit 7 / Receive Remote Alarm Condition Clear (RRAIC). Change of state indication. Set when a RRAI condition has cleared (falling edge detect of RRAI). 166 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 RRAIC 0 RIM1 Receive Interrupt Mask Register 1 0A0h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 RAISC 0 5 RLOSC 0 4 RLOFC 0 3 RRAID 0 2 RAISD 0 1 RLOSD 0 0 RLOFD 0 Bit 0 / Receive Loss of Frame Detect (RLOFD) 0 = interrupt masked 1 = interrupt enabled Bit 1 / Receive Loss of Signal Detect (RLOSD) 0 = interrupt masked 1 = interrupt enabled Bit 2 / Receive AIS Detect (RAISD) 0 = interrupt masked 1 = interrupt enabled Bit 3 / Receive Remote Alarm Detect (RRAID) 0 = interrupt masked 1 = interrupt enabled Bit 4 / Receive Loss of Frame Clear (RLOFC) 0 = interrupt masked 1 = interrupt enabled Bit 5 / Receive Loss of Signal Clear (RLOSC) 0 = interrupt masked 1 = interrupt enabled Bit 6 / Receive AIS Clear (RAISC) 0 = interrupt masked 1 = interrupt enabled Bit 7 / Receive Remote Alarm Clear (RRAIC) 0 = interrupt masked 1 = interrupt enabled 167 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 RLS2 Receive Latched Status Register 2 091h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 CRCRC 0 5 CASRC 0 4 FASRC 0 3 RSA1 0 2 RSA0 0 1 RCMF 0 0 RAF 0 All bits in this register are latched. Bits 0 to 3 can cause interrupts. There is no associated real-time register. Bit 0 / Receive Align Frame Event (RAF). Set every 250ms at the beginning of align frames. Used to alert the host that Si and Sa bits are available in the RAF and RNAF registers. Bit 1 / Receive CRC4 Multiframe Event (RCMF). Set on CRC4 multiframe boundaries; will continue to be set every 2ms on an arbitrary boundary if CRC4 is disabled. Bit 2 / Receive Signaling All Zeros Event (RSA0). Set when over a full MF, time slot 16 contains all zeros. Bit 3 / Receive Signaling All Ones Event (RSA1). Set when the contents of time slot 16 contain less than three zeros over 16 consecutive frames. This alarm is not disabled in the CCS signaling mode. Bit 4 / FAS Resync Criteria Met Event (FASRC). Set when 3 consecutive FAS words are received in error. Bit 5 / CAS Resync Criteria Met Event (CASRC). Set when 2 consecutive CAS MF alignment words are received in error. Bit 6 / CRC Resync Criteria Met Event (CRCRC). Set when 915/1000 codewords are received in error. Bit 7 / Unused 168 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 RIM2 Receive Interrupt Mask Register 2 0A1h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 -- 0 4 -- 0 3 RSA1 0 2 RSA0 0 1 RCMF 0 0 RAF 0 Bit 0 / Receive Align Frame Event (RAF) 0 = interrupt masked 1 = interrupt enabled Bit 1 / Receive CRC4 Multiframe Event (RCMF) 0 = interrupt masked 1 = interrupt enabled Bit 2 / Receive Signaling All Zeros Event (RSA0) 0 = interrupt masked 1 = interrupt enabled Bit 3 / Receive Signaling All Ones Event (RSA1) 0 = interrupt masked 1 = interrupt enabled Bits 4 to 7 / Unused. Must be set = 0 for proper operation. Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 RRTS3 Receive Real-Time Status Register 3 0B2h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 -- 0 4 -- 0 3 LORC 0 2 -- 0 1 V52LNK 0 0 RDMA 0 All bits in this register are real-time (not latched). Bit 0 / Receive Distant MF Alarm Condition (RDMA). Set when bit-6 of time slot 16 in frame 0 has been set for two consecutive multiframes. This alarm is not disabled in the CCS signaling mode. Bit 1 / V5.2 Link Detected Condition (V52LNK). Set on detection of a V5.2 link identification signal. (G.965). Bits 2, 4 to 7 / Unused. Bit 3 / Loss of Receive Clock Condition (LORC). Set when the RCLK pin has not transitioned for one channel time. 169 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: RLS3 Receive Latched Status Register 3 092h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 Bit # 7 6 5 4 3 Name LORCC -- V52LNKC RDMAC LORCD Default 0 0 0 0 0 All bits in this register are latched and can create interrupts. 2 -- 0 1 V52LNKD 0 0 RDMAD 0 Bit 0 / Receive Distant MF Alarm Detect (RDMAD). Change of state indication. Set when bit 6 of time slot 16 in frame 0 has been set for two consecutive multiframes. This alarm is not disabled in the CCS signaling mode. This is the rising edge detect of RDMA. Bit 1 / V5.2 Link Detect (V52LNKD). Change of state indication. Set on detection of a V5.2 link identification signal. (G.965). This is the rising edge detect of V52LNK. Bits 2, 6 / Unused Bit 3 / Loss of Receive Clock Detect (LORCD). Change of state indication. Set when the RCLK pin has not transitioned for one channel time (rising edge detect of LORC). Bit 4 / Receive Distant MF Alarm Clear (RDMAC). Change of state indication. Set when a RDMA condition has cleared (falling edge detect of RDMA). Bit 5 / V5.2 Link Detected Clear (V52LNKC). Change of state indication. Set when a V52LNK condition has cleared (falling edge detect of V52LNK). Bit 7 / Loss of Receive Clock Clear (LORCC). Change of state indication. Set when a LORC condition has cleared (falling edge detect of LORC). 170 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 LORCC 0 RIM3 Receive Interrupt Mask Register 3 0A2h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 V52LNKC 0 4 RDMAC 0 3 LORCD 0 2 -- 0 1 V52LNKD 0 0 RDMAD 0 Bit 0 / Receive Distant MF Alarm Detect (RDMAD) 0 = interrupt masked 1 = interrupt enabled Bit 1 / V5.2 Link Detect (V52LNKD) 0 = interrupt masked 1 = interrupt enabled Bits 2, 6 / Unused. Must be set = 0 for proper operation. Bit 3 / Loss of Receive Clock Detect (LORCD) 0 = interrupt masked 1 = interrupt enabled Bit 4 / Receive Distant MF Alarm Clear (RDMAC) 0 = interrupt masked 1 = interrupt enabled Bit 5 / V5.2 Link Detected Clear (V52LNKC) 0 = interrupt masked 1 = interrupt enabled Bit 7 / Loss of Receive Clock Clear (LORCC) 0 = interrupt masked 1 = interrupt enabled 171 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 CSC5 0 RRTS7 Receive Real-Time Status Register 7 062h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 CSC4 0 5 CSC3 0 4 CSC2 0 3 CSC0 0 2 CRC4SA 0 1 CASSA 0 0 FASSA 0 All bits in this register are real-time (not latched). Bit 0 / FAS Sync Active (FASSA). Set while the synchronizer is searching for alignment at the FAS level. Bit 1 / CAS MF Sync Active (CASSA). Set while the synchronizer is searching for the CAS MF alignment word. Bit 2 / CRC4 MF Sync Active (CRC4SA). Set while the synchronizer is searching for the CRC4 MF alignment word. Bits 3 to 7 / CRC4 Sync Counter Bits (CSC0 and CSC2 to CSC4). The CRC4 Sync Counter increments each time the 8ms CRC4 multiframe search times out. The counter is cleared when the framer has successfully obtained synchronization at the CRC4 level. The counter can also be cleared by disabling the CRC4 mode (RCR1.3 = 0). This counter is useful for determining the amount of time the framer has been searching for synchronization at the CRC4 level. ITU G.706 suggests that if synchronization at the CRC4 level cannot be obtained within 400ms, then the search should be abandoned and proper action taken. The CRC4 Sync Counter rolls over. CSC0 is the LSB of the 6-bit counter. (Note: The next to LSB is not accessible. CSC1 is omitted to allow resolution to >400ms using 5 bits.) 172 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 RESF 0 RLS4 Receive Latched Status Register 4 093h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 RESEM 0 5 RSLIP 0 4 --0 3 RSCOS 0 2 1SEC 0 1 TIMER 0 0 RMF 0 All bits in this register are latched. There is no associated real-time register. Bit 0 / Receive Multiframe Event (RMF). Set every 2.0ms on receive CAS multiframe boundaries to alert host the signaling data is available. Continues to set on an arbitrary 2.0ms boundary when CAS signaling is not enabled. Bit 1 / Timer Event (TIMER). Follows the error counter update interval as determined by the ECUS bit in the Error Counter Configuration Register (ERCNT). T1: Set on increments of 1 second or 42ms based on RCLK. E1: Set on increments of 1 second or 62.5ms based on RCLK. Bit 2 / One-Second Timer (1SEC). Set on every one-second interval based on RCLK. Bit 3 / Receive Signaling Change Of State Event (RSCOS). Set when any channel selected by the Receive Signaling Change Of State Interrupt Enable registers (RSCSE1 through RSCSE3), changes signaling state. Bit 4 / Unused Bit 5 / Receive Elastic Store Slip Occurrence Event (RSLIP). Set when the receive elastic store has either repeated or deleted a frame. Bit 6 / Receive Elastic Store Empty Event (RESEM). Set when the receive elastic store buffer empties and a frame is repeated. Bit 7 / Receive Elastic Store Full Event (RESF). Set when the receive elastic store buffer fills and a frame is deleted. 173 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 RESF 0 RIM4 Receive Interrupt Mask Register 4 0A3h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 RESEM 0 5 RSLIP 0 4 -- 0 3 RSCOS 0 2 1SEC 0 1 TIMER 0 0 RMF 0 Bit 0 / Receive Multiframe Event (RMF) 0 = interrupt masked 1 = interrupt enabled Bit 1 / Timer Event (TIMER) 0 = interrupt masked 1 = interrupt enabled Bit 2 / One-Second Timer (1SEC) 0 = interrupt masked 1 = interrupt enabled Bit 3 / Receive Signaling Change Of State Event (RSCOS) 0 = interrupt masked 1 = interrupt enabled Bit 4 / Unused. Must be set = 0 for proper operation. Bit 5 / Receive Elastic Store Slip Occurrence Event (RSLIP) 0 = interrupt masked 1 = interrupt enabled Bit 6 / Receive Elastic Store Empty Event (RESEM) 0 = interrupt masked 1 = interrupt enabled Bit 7 / Receive Elastic Store Full Event (RESF) 0 = interrupt masked 1 = interrupt enabled 174 DS26401 Octal T1/E1/J1 Framer 10.8 E1 Error Count Registers The DS26401 contains four counters that are used to accumulate line coding errors, path errors, and synchronization errors. Counter update options include one-second boundaries, 42ms (T1 mode only), 62.5ms (E1 mode only), or manually. See Error Counter Configuration Register (ERCNT). When updated automatically, the user can use the interrupt from the timer to determine when to read these registers. All four counters will saturate at their respective maximum counts and they will not rollover. The Line-Code Violation Count Register has the potential to saturate, but the bit error would have to exceed 10E-2 before this would occur. All other counters will roll over. Several options are available for latching the performance counters: 1) Each framer's counters are latched independently based on independent one-second interval timers. 2) Each framer's counters are latched independently based on independent 62.5ms interval timers. 3) Each framer's counters are latched independently with a low to high transition on the respective MECU control bit. 4) Counters from selected framers are latched synchronously at the one-second interval supplied by framer_#1. 5) Counters from selected framers are synchronously latched manually with the Global Counter Latch Enable (GCLE) bit in GCR1. The following table shows configuration bit settings in the ERCNT register for each of the 5 modes mentioned above: Control Bit EAMS ECUS MECU MCUS 1SECS Mode 1 0 0 0 0 0 Mode 2 0 1 0 0 0 Mode 3 1 X 0 to 1 0 0 Mode 4 0 0 0 0 1 Mode 5 1 0 0 1 0 175 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 1SECS 0 ERCNT Error Counter Configuration Register 086h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 MCUS 0 5 MECU 0 4 ECUS 0 3 EAMS 0 2 -- 0 1 -- 0 0 LCVCRF 0 Bit 0 / E1 Line Code Violation Count Register Function Select (LCVCRF) 0 = do not count excessive zeros 1 = count excessive zeros Bits 1, 2 / Unused. Must be set = 0 for proper operation. Bit 3 / Error Accumulation Mode Select (EAMS) 0 = ERCNT.4 determines accumulation time (timed update) 1 = ERCNT.5 determines accumulation time (manual update) Bit 3 / Error Accumulation Mode Select (EAMS) 0 = ERCNT.4 determines accumulation time (timed update) 1 = ERCNT.5 determines accumulation time (manual update) Bit 4 / Error Counter Update Select (ECUS) T1 mode: 0 = Update error counters once a second 1 = Update error counters every 42ms (336 frames) E1 mode: 0 = Update error counters once a second 1 = Update error counters every 62.5ms (500 frames) Bit 5 / Manual Error Counter Update (MECU). When enabled by ERCNT.3, the changing of this bit from a 0 to a 1 allows the next clock cycle to load the error counter registers with the latest counts and reset the counters. The user must wait a minimum of 250ms before reading the error count registers to allow for proper update. Bit 6 / Manual Counter Update Select (MCUS). When manual update mode is enabled with EAMS, this bit can be used to allow the GLCE bit in GCR1 to latch all counters. Useful for synchronously latching counters of multiple framers. 0 = MECU is used to manually latch counters. 1 = GLCE is used to manually latch counters. Bit 7 / One-Second Select (1SECS). When timed update is enabled by EAMS, setting this bit for a specific framer will allow that framer's counters to latch on the one-second reference from framer #1. Note that this bit should always be clear for framer #1. 0 = Use internally generated one-second timer. 1 = Use 1 second timer from framer #1. 176 DS26401 Octal T1/E1/J1 Framer 10.8.1 E1 Line Code Violation Count Register (LCVCR) Either bipolar violations or code violations can be counted. Bipolar violations are defined as consecutive marks of the same polarity. In this mode, if the HDB3 mode is set for the receive side, HDB3 codewords are not counted as BPVs. If ERCNT.0 is set, then the LVC counts code violations as defined in ITU O.161. Code violations are defined as consecutive bipolar violations of the same polarity. In most applications, the framer should be programmed to count BPVs when receiving AMI code and to count CVs when receiving HDB3 code. This counter increments at all times and is not disabled by loss of sync conditions. The counter saturates at 65,535 and will not rollover. The bit error rate on an E1 line would have to be greater than 10** - 2 before the VCR would saturate. See Table 10-3. Table 10-3. E1 Line Code Violation Counting Options E1 CODE VIOLATION SELECT (ERCNT.0) 0 1 WHAT IS COUNTED IN THE LCVCRs BPVs CVs Register Name: Register Description: Register Address: Bit # Name Default 7 LCVC15 0 LCVCR1 Line Code Violation Count Register 1 050h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 LCVC14 0 5 LCVC13 0 4 LCVC12 0 3 LCVC11 0 2 LCVC10 0 1 LCVC9 0 0 LCCV8 0 Bits 0 to 7 / Line Code Violation Counter Bits 8 to 15 (LCVC8 to LCVC15). LCV15 is the MSB of the 16-bit code violation count. Register Name: Register Description: Register Address: Bit # Name Default 7 LCVC7 0 LCVCR2 Line Code Violation Count Register 2 051h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 LCVC6 0 5 LCVC5 0 4 LCVC4 0 3 LCVC3 0 2 LCVC2 0 1 LCVC1 0 0 LCVC0 0 Bits 0 to 7 / Line Code Violation Counter Bits 0 to 7 (LCVC0 to LCVC7). LCV0 is the LSB of the 16-bit code violation count. 177 DS26401 Octal T1/E1/J1 Framer 10.8.2 E1 Path Code Violation Count Register (PCVCR) In E1 operation, the Path Code Violation Count register records CRC4 errors. Since the maximum CRC4 count in a one-second period is 1000, this counter cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC4 level; it will continue to count if loss of multiframe sync occurs at the CAS level. The Path Code Violation Count Register 1 (PCVCR1) is the most significant word and PCVCR2 is the least significant word of a 16-bit counter that records path violations (PVs). Register Name: Register Description: Register Address: Bit # Name Default 7 PCVC15 0 PCVCR1 Path Code Violation Count Register 1 052h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 PCVC14 0 5 PCVC13 0 4 PCVC12 0 3 PCVC11 0 2 PCVC10 0 1 PCVC9 0 0 PCVC8 0 Bits 0 to 7 / Path Code Violation Counter Bits 8 to 15 (PCVC8 to PCVC15). PCVC15 is the MSB of the 16-bit path code violation count. Register Name: Register Description: Register Address: Bit # Name Default 7 PCVC7 0 PCVCR2 Path Code Violation Count Register 2 053h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 PCVC6 0 5 PCVC5 0 4 PCVC4 0 3 PCVC3 0 2 PCVC2 0 1 PCVC1 0 0 PCVC0 0 Bits 0 to 7 / Path Code Violation Counter Bits 0 to 7 (PCVC0 to PCVC7). PCVC0 is the LSB of the 16-bit path code violation count. 178 DS26401 Octal T1/E1/J1 Framer 10.8.3 E1 Frames Out-of-Sync Count Register (FOSCR) In E1 mode, the FOSCR counts word errors in the Frame Alignment Signal in time slot 0. This counter is disabled when RLOF is high. FAS errors will not be counted when the framer is searching for FAS alignment and/or synchronization at either the CAS or CRC4 multiframe level. Since the maximum FAS word error count in a onesecond period is 4000, this counter cannot saturate. The Frames Out of Sync Count Register 1 (FOSCR1) is the most significant word and FOSCR2 is the least significant word of a 16-bit counter that records frames out of sync. Register Name: Register Description: Register Address: Bit # Name Default 7 FOS15 0 FOSCR1 Frames Out Of Sync Count Register 1 054h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 FOS14 0 5 FOS13 0 4 FOS12 0 3 FOS11 0 2 FOS10 0 1 FOS9 0 0 FOS8 0 Bits 0 to 7 / Frames Out of Sync Counter Bits 8 to 15 (FOS8 to FOS15). FOS15 is the MSB of the 16-bit frames out of sync count. Register Name: Register Description: Register Address: Bit # Name Default 7 FOS7 0 FOSCR2 Frames Out Of Sync Count Register 2 055h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 FOS6 0 5 FOS5 0 4 FOS4 0 3 FOS3 0 2 FOS2 0 1 FOS1 0 0 FOS0 0 Bits 0 to 7 / Frames Out of Sync Counter Bits 0 to 7 (FOS0 to FOS7). FOS0 is the LSB of the 16-bit frames out of sync count. 179 DS26401 Octal T1/E1/J1 Framer 10.8.4 E-Bit Counter (EBCR) This counter is only available in E1 mode. E-bit Count Register 1 (EBCR1) is the most significant word and EBCR2 is the least significant word of a 16-bit counter that records Far End Block Errors (FEBE) as reported in the first bit of frames 13 and 15 on E1 lines running with CRC4 multiframe. These count registers will increment once each time the received E-bit is set to zero. Since the maximum E-bit count in a one second period is 1000, this counter cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC4 level; it will continue to count if loss of multiframe sync occurs at the CAS level. Register Name: Register Description: Register Address: Bit # Name Default 7 EB15 0 EBCR1 E-Bit Count Register 1 056h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 EB14 0 5 EB13 0 4 EB12 0 3 EB11 0 2 EB10 0 1 EB9 0 0 EB8 0 Bits 0 to 7 / E-Bit Counter Bits 8 to 15 (EB8 to EB15). EB15 is the MSB of the 16-bit E-Bit count. Register Name: Register Description: Register Address: Bit # Name Default 7 EB7 0 EBCR2 E-Bit Count Register 2 057h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 EB6 0 5 EB5 0 4 EB4 0 3 EB3 0 2 EB2 0 1 EB1 0 0 EB0 0 Bits 0 to 7 / E-Bit Counter Bits 0 to 7 (EB0 to EB7). EB0 is the LSB of the 16-bit E-Bit count. 180 DS26401 Octal T1/E1/J1 Framer 10.9 DS0 Monitoring Function The DS26401 has the ability to monitor one DS0 64kbps channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the receive direction, the RCM0 to RCM4 bits in the RDS0SEL register need to be properly set and the DS0 channel pointed to by the RCM0 to RCM4 bits will appear in the Receive DS0 (RDS0M) register. The RCM0 to RCM4 bits should be programmed with the decimal decode of the appropriate E1 channel. E1 channels 1 through 32 map to register values 0 through 31. For example, if DS0 channel 15 in the receive direction needed to be monitored, then the following values would be programmed into RDS0SEL: RCM4 = 0 RCM3 = 1 RCM2 = 1 RCM1 = 1 RCM0 = 0 Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 RDS0SEL Receive Channel Monitor Select 012h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 -- 0 4 RCM4 0 3 RCM3 0 2 RCM2 0 1 RCM1 0 0 RCM0 0 Bits 0 to 4 / Receive Channel Monitor Bits (RCM0 to RCM4). RCM0 is the LSB of a 5-bit channel select that determines which receive DS0 channel data will appear in the RDS0M register. Bits 5 to 7 / Unused. Must be set = 0 for proper operation. Register Name: Register Description: Register Address: Bit # Name Default 7 B1 0 RDS0M Receive DS0 Monitor Register 060h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 B2 0 5 B3 0 4 B4 0 3 B5 0 2 B6 0 1 B7 0 0 B8 0 Bits 0 to 7 / Receive DS0 Channel Bits (B1 to B8). Receive channel data that has been selected by the Receive Channel Monitor Select Register. B8 is the LSB of the DS0 channel (last bit to be received). 181 DS26401 Octal T1/E1/J1 Framer 10.10 E1 Receive Signaling Operation There are two methods to access receive signaling data--processor-based (i.e., software-based) or hardware based. Processor-based refers to access through the transmit and receive signaling registers, RS1-RS16. Hardware-based refers to the RSIG pin. Both methods can be used simultaneously. 10.10.1 Processor-Based Signaling Signaling data is sampled in the receive data stream and copied into the receive signaling registers, RS1 through RS16.. The signaling information in these registers is always updated on multiframe boundaries. This function is always enabled. 10.10.2 Change Of State In order to avoid constantly monitoring of the receive signaling registers the DS26401 can be programmed to alert the host when any specific channel or channels undergo a change of their signaling state. RSCSE1 through RSCSE4 for E1 are used to select which channels can cause a change of state indication. The change of state is indicated in Latched Status Register 4 (RLS4.3). If signaling integration is enabled then the new signaling state must be constant for 3 multiframes before a change of state indication is indicated. The user can enable the INT pin to toggle low upon detection of a change in signaling by setting the appropriate interrupt mask bit RIM4.3. The signaling integration mode is global and cannot be enabled on a channel-by-channel basis. The user can identity which channels have undergone a signaling change of state by reading the Receive Signaling Status (RSS1 through RSS4) registers. The information from these registers tell the user which RSx register to read for the new signaling data. All changes are indicated in the RSS1-RSS4 registers regardless of the RSCSE1- RSCSE4 registers. 10.10.3 Hardware-Based Receive Signaling In hardware based signaling the signaling data can be obtained from the RSER pin or the RSIG pin. RSIG is a signaling PCM stream output on a channel-by-channel basis from the signaling buffer. The E1 TS16 signaling data is still present in the original data stream at RSER. The signaling buffer provides signaling data to the RSIG pin and also allows signaling data to be re-inserted into the original data stream in a different alignment that is determined by a multiframe signal from the RSYNC pin. In this mode, the receive elastic store may be enabled or disabled. If the receive elastic store is enabled, then the backplane clock (RSYSCLK) can be either 1.544 MHz or 2.048MHz. If IBO mode is enabled then RSYSCLK may also be 4.096MHz, 8.192MHz, or 16.384MHz. The ABCD signaling bits are output on RSIG in the lower nibble of each channel. The RSIG data is updated once per CAS multiframe (2ms) unless a freeze is in effect. See the timing diagrams in Section 13.4 for some examples. 182 DS26401 Octal T1/E1/J1 Framer 10.10.4 Signaling Debounce When signaling integration is enabled the signaling data at RSIG is automatically debounced. Signaling must be constant for three multiframes before being up-dated at RSIG. Signaling debounce is enabled on a global basis. 10.10.5 Receive Signaling Reinsertion at RSER In this mode, the user will provide a multiframe sync at the RSYNC pin and the signaling data will be reinserted based on this alignment. In T1 mode, this results in two copies of the signaling data in the RSER data stream. The original signaling data based on the Fs/ESF frame positions and the realigned data based on the user supplied multiframe sync applied at RSYNC. In voice channels this extra copy of signaling data is of little consequence. Reinsertion can be avoided in data channels since this feature is activated on a per-channel basis. For reinsertion, the elastic store must be enabled, however, the backplane clock can be either 1.544MHz or 2.048MHz. Signaling reinsertion mode is enabled, on a per-channel basis by setting the Receive Signaling Re-insertion Channel Select bit high in the RSI register. The channels that are to have signaling reinserted are selected by writing to the RSI1-RSI4 registers. In E1 mode, the user will generally select all channels or none for reinsertion. 10.10.6 Receive Signaling Freeze The signaling data in the four multiframe signaling buffer will be frozen in a known good state upon either a loss of synchronization (OOF event), carrier loss, or change of frame alignment. To allow this freeze action to occur, the RSFE control bit (RSIGC.1) should be set high. The user can force a freeze by setting the RSFF control bit (RSIGC.2) high. The RSIGF output pin provides a hardware indication that a freeze is in effect. The four multiframe buffer provides a three multiframe delay in the signaling bits provided at the RSIG pin (and at the RSER pin if Receive Signaling Reinsertion is enabled). When freezing is enabled (RSFE = 1), the signaling data will be held in the last known good state until the corrupting error condition subsides. When the error condition subsides, the signaling data will be held in the old state for at least an additional 6ms before being allowed to be updated with new signaling data. 183 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 RSIGC Receive Signaling Control Register 013h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 -- 0 4 CASMS 0 3 -- 0 2 RSFF 0 1 RSFE 0 0 RSIE 0 Bit 0 / Receive Signaling Integration Enable (RSIE) 0 = signaling changes of state reported on any change in selected channels 1 = signaling must be stable for 3 multiframes in order for a change of state to be reported Bit 1 / Receive Signaling Freeze Enable (RSFE) 0 = no freezing of receive signaling data will occur 1 = allow freezing of receive signaling data at RSIG (and RSER if Receive Signaling Re-insertion is enabled). Bit2 / Receive Signaling Force Freeze (RSFF). Freezes receive-side signaling at RSIG (and RSER if Receive Signaling Reinsertion is enabled); will override Receive Freeze Enable (RFE). 0 = do not force a freeze event 1 = force a freeze event Bits 3, 5 to 7 / Unused. Must be set = 0 for proper operation. Bit 4 / CAS Mode Select (CASMS) 0 = The DS26401 will initiate a resync when two consecutive multiframe alignment signals have been received with an error. 1 = The DS26401 will initiate a resync when two consecutive multiframe alignment signals have been received with an error, or 1 multiframe has been received with all the bits in time slot 16 in state 0. Alignment criteria is met when at least one bit in state 1 is present in the time slot 16 preceding the multiframe alignment signal first detected (G.732 alternate criteria). 184 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: RS1 to RS16 Receive Signaling Registers 040h to 04Fh [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8] The Receive Signaling Registers are frozen and not updated during a loss of sync condition.They contain the most recent signaling information before the LOF occurred. (MSB) 0 CH1-A CH2-A CH3-A CH4-A CH5-A CH6-A CH7-A CH8-A CH9-A CH10-A CH11-A CH12-A CH13-A CH14-A CH15-A (LSB) X CH16-D CH17-D CH18-D CH19-D CH20-D CH21-D CH22-D CH23-D CH24-D CH25-D CH26-D CH27-D CH28-D CH29-D CH30-D 0 CH1-B CH2-B CH3-B CH4-B CH5-B CH6-B CH7-B CH8-B CH9-B CH10-B CH11-B CH12-B CH13-B CH14-B CH15-B 0 CH1-C CH2-C CH3-C CH4-C CH5-C CH6-C CH7-C CH8-C CH9-C CH10-C CH11-C CH12-C CH13-C CH14-C CH15-C 0 CH1-D CH2-D CH3-D CH4-D CH5-D CH6-D CH7-D CH8-D CH9-D CH10-D CH11-D CH12-D CH13-D CH14-D CH15-D X CH16-A CH17-A CH18-A CH19-A CH20-A CH21-A CH22-A CH23-A CH24-A CH25-A CH26-A CH27-A CH28-A CH29-A CH30-A Y CH16-B CH17-B CH18-B CH19-B CH20-B CH21-B CH22-B CH23-B CH24-B CH25-B CH26-B CH27-B CH28-B CH29-B CH30-B X CH16-C CH17-C CH18-C CH19-C CH20-C CH21-C CH22-C CH23-C CH24-C CH25-C CH26-C CH27-C CH28-C CH29-C CH30-C RS1 RS2 RS3 RS4 RS5 RS6 RS7 RS8 RS9 RS10 RS11 RS12 RS13 RS14 RS15 RS16 Register Name: Register Description: Register Address: RSS1, RSS2, RSS3, RSS4 Receive Signaling Status Registers 098h, 099h, 09Ah, 09ABh [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8] When a channel's signaling data changes state, the respective bit in registers RSS1-RSS4 will be set and latched. The RSCOS bit (RLSR4.3) will be set if the channel was also enabled by setting the appropriate bit in RSCSE1-4. The INT signal will go low if enabled by the interrupt mask bit RIM4.3. The bit will remain set until read. Note that in CAS mode, the LSB of RSS1 would typically represent the CAS alignment bits, and the LSB of RSS3 represents reserved bits and the distant multiframe alarm. (MSB) CH8 CH16 CH24 CH32 (LSB) CH1* CH9 CH17* CH25 CH7 CH15 CH23 CH31 CH6 CH14 CH22 CH30 CH5 CH13 CH21 CH29 CH4 CH12 CH20 CH28 CH3 CH11 CH19 CH27 CH2 CH10 CH18 CH26 RSS1 RSS2 RSS3 RSS4 Status bits in this register are latched. 185 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: RSCSE1, RSCSE2, RSCSE3, RSCSE4 Receive Signaling Change of State Enable 0A8h, 0A9h, 0AAH, 0ABh [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8] Setting any of the CH1 through CH32 bits in the RSCSE1 through RSCSE4 registers cause RSCOS (RLSR4.3) to be set when that channel's signaling data changes state. (MSB) CH8 CH16 CH24 CH32 (LSB) CH1* CH9 CH17* CH25 CH7 CH15 CH23 CH31 CH6 CH14 CH22 CH30 CH5 CH13 CH21 CH29 CH4 CH12 CH20 CH28 CH3 CH11 CH19 CH27 CH2 CH10 CH18 CH26 RSCSE1 RSCSE2 RSCSE3 RSCSE4 Register Name: Register Description: Register Address: RSI1, RSI2, RSI3, RSI4 Receive Signaling Reinsertion Enable Registers 0C8h, 0C9h, 0CAh, 0CBh [+ (200h * n) :where n= 0to7, for Ports 1to8] Setting any of the CH1 through CH32 bits in the RSI1 through RSI4 registers cause signaling data to be reinserted for the associated channel. (MSB) CH8 CH16 CH24 CH32 (LSB) CH1 CH9 CH17 CH25 CH7 CH15 CH23 CH31 CH6 CH14 CH22 CH30 CH5 CH13 CH21 CH29 CH4 CH12 CH20 CH28 CH3 CH11 CH19 CH27 CH2 CH10 CH18 CH26 RSI1 RSI2 RSI3 RSI4 186 DS26401 Octal T1/E1/J1 Framer 10.11 E1 Receive Per-Channel Idle Code Insertion Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions. Thirtytwo Receive Idle Definition Registers (RIDR1-RIDR32) are provided to set the 8-bit idle code for each channel. The Receive Channel Idle Code Enable registers (RCICE1-4) are used to enable idle code replacement on a per channel basis. Register Name: Register Description: Register Address: Bit # Name Default 7 C7 0 RIDR1 to RIDR32 Receive Idle Code Definition Registers 1 to 32 020h to 03Fh [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8] 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Bits 0 to 7 / Per-Channel Idle Code Bits (C0 to C7). C0 is the LSB of the Code (this bit is transmitted last). Address 20H is for channel 1, address 3FH is for channel 32. The Receive Channel Idle Code Enable Registers (RCICE1/2/3/4) are used to determine which of the 32 E1 channels from the E1 line to the backplane should be overwritten with the code placed in the Receive Idle Code Definition Register. Register Name: Register Description: Register Address: (MSB) CH8 CH16 CH24 CH32 RCICE1, RCICE2, RCICE3, RCICE4 Receive Channel Idle Code Enable Registers 0D0h, 0D1h, 0D2h, 0D3h [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8] (LSB) CH1 CH9 CH17 CH25 CH7 CH15 CH23 CH31 CH6 CH14 CH22 CH30 CH5 CH13 CH21 CH29 CH4 CH12 CH20 CH28 CH3 CH11 CH19 CH27 CH2 CH10 CH18 CH26 RCICE1 RCICE2 RCICE3 RCICE4 Bits 0 to 7 / Receive Channels 1 to 32 Code Insertion Control Bits (CH1 to CH32) 0 = do not insert data from the Idle Code Array into the receive data stream 1 = insert data from the Idle Code Array into the receive data stream 187 DS26401 Octal T1/E1/J1 Framer 10.12 Receive Channel Blocking Operation The Receive Channel blocking Registers (RCBR1 / RCBR2 / RCBR3 / RCBR4) and the Transmit Channel Blocking Registers (TCBR1 / TCBR2 / TCBR3 / TCBR4) control the RCHBLK and TCHBLK pins respectively. The RCHBLK and TCHBLK pins are user programmable outputs that can be forced high or low during individual channels. These outputs can be used to block clocks to a USART or LAPD controller in ISDN-PRI applications. When the appropriate bits are set to a one, the RCHBLK and TCHBLK pin will be held high during the entire corresponding channel time. Register Name: Register Description: Register Address: RCBR1, RCBR2, RCBR3, RCBR4 Receive Channel Blocking Registers 0C4h, 0C5h, 0C6h, 0C7h [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8] (LSB) CH1 CH9 CH17 CH25 (MSB) CH8 CH16 CH24 CH32 CH7 CH15 CH23 CH31 CH6 CH14 CH22 CH30 CH5 CH13 CH21 CH29 CH4 CH12 CH20 CH28 CH3 CH11 CH19 CH27 CH2 CH10 CH18 CH26 RCBR1 RCBR2 RCBR3 RCBR4 Bits 0 to 7 / Receive Channels 1 to 32 Channel Blocking Control Bits (CH1 to CH32) 0 = force the RCHBLK pin to remain low during this channel time 1 = force the RCHBLK pin high during this channel time 188 DS26401 Octal T1/E1/J1 Framer 10.13 Receive Elastic Stores Operation The DS26401 contains dual two-frame elastic stores, one for the receive direction, and one for the transmit direction. Both elastic stores are fully independent. The transmit and receive side elastic stores can be enabled/disabled independent of each other. Also, each elastic store can interface to either a 1.544MHz or 2.048/4.096/8.192/16.384MHz backplane without regard to the backplane rate of the other elastic store. The elastic stores have two main purposes. First, they can be used for rate conversion. When the DS26401 is in the T1 mode, the elastic stores can rate convert the T1 data stream to a 2.048MHz backplane. In E1 mode, the elastic store can rate convert the E1 data stream to a 1.544MHz backplane. Secondly, they can be used to absorb the differences in frequency and phase between the T1 or E1 data stream and an asynchronous (i.e., not locked) backplane clock (which can be 1.544MHz or 2.048MHz). In this mode, the elastic stores will manage the rate difference and perform controlled slips, deleting or repeating frames of data in order to manage the difference between the network and the backplane. If the elastic store is enabled, then either CAS or CRC4 multiframe boundaries will be indicated via the RMSYNC output as controlled by the RSMS2 control bit (RIOCR.1). If the user selects to apply a 1.544 MHz clock to the RSYSCLK pin, then the RBCS registers will determine which channels of the received E1 data stream will be deleted. In this mode an F-bit location is inserted into the RSER data and set to one. Also, in 1.544 MHz applications, the RCHBLK output will not be active in Channels 25 through 32 (or in other words, RCBR4 is not active). If the two-frame elastic buffer either fills or empties, a controlled slip will occur. If the buffer empties, then a full frame of data will be repeated at RSER and the RLS4.5 and RLS4.6 bits will be set to a one. If the buffer fills, then a full frame of data will be deleted and the RLS4.5 and RLS4.7 bits will be set to a one. The elastic stores can also be used to multiplex T1 or E1 data streams into higher backplane rates. This is the Interleave Bus Option (IBO) which is discussed in Section 10.17. 189 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 RDATFMT RESCR Receive Elastic Store Control Register 085h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 RGCLKEN 5 -- 4 RSZS 3 RESALGN 2 RESR 1 RESMDM 0 RESE 0 0 0 0 0 0 0 0 Bit 0 / Receive Elastic Store Enable (RESE) 0 = elastic store is bypassed 1 = elastic store is enabled Bit 1 / Receive Elastic Store Minimum Delay Mode (RESMDM) 0 = elastic stores operate at full two frame depth 1 = elastic stores operate at 32-bit depth Bit 2 / Receive Elastic Store Reset (RESR). Setting this bit from a zero to a one will force the read pointer into the same frame that the write pointer is exiting, minimizing the delay through the elastic store. If this command should place the pointers within the slip zone (see bit 4), then an immediate slip will occur and the pointers will move back to opposite frames. Should be toggled after RSYSCLK has been applied and is stable. Do not leave this bit set HIGH. Bit 3 / Receive Elastic Store Align (RESALGN). Setting this bit from a zero to a one will force the receive elastic store's write/read pointers to a minimum separation of half a frame. No action will be taken if the pointer separation is already greater or equal to half a frame. If pointer separation is less than half a frame, the command will be executed and the data will be disrupted. Should be toggled after RSYSCLK has been applied and is stable. Must be cleared and set again for a subsequent align. Bit 4 / Receive Slip Zone Select (RSZS). This bit determines the minimum distance allowed between the elastic store read and write pointers before forcing a controlled slip. This bit is only applies during T1 to E1 or E1 to T1 conversion applications. 0 = force a slip at 9 bytes or less of separation (used for clustered blank channels) 1 = force a slip at 2 bytes or less of separation (used for distributed blank channels) Bit 5 / Unused. Must be set = 0 for proper operation. Bit 6 / Receive Gapped Clock Enable (RGPCKEN) 0 = RCHCLK functions normally 1 = Enable gapped bit clock output on RCHCLK Bit 7 / Receive Channel Data Format (RDATFMT) 0 = 64kbps (data contained in all 8 bits) 1 = 56kbps (data contained in 7 out of the 8 bits) RGPCKEN and RDATFMT are not associated with the elastic store and will be explained in the fractional support section. 190 DS26401 Octal T1/E1/J1 Framer 10.13.1 Mapping E1 Channels Onto a 1.544MHz Backplane The user can use the RSCLKM bit in RIOCR.4 to enable the receive elastic store to operate with a 1.544MHz backplane (24 channels / frame + F-bit). In this mode, the user can chose which of the E1 time slots will be ignored (not transmitted onto RSER) by programming the Receive Blank Channel Select registers (RBCS1-4). A logic 1 in the associated bit location will cause the DS26401 elastic store to ignore the incoming E1 data for that channel. Typically the user will want to program eight channels to be ignored. The default (power-up) configuration will ignore channels 25 to 32, so that the first 24 E1 channels are mapped into the 24 channels of the 1.544MHz backplane. In this mode the F-bit location at RSER is always set to 1. For example, if the user wants to ignore E1 time slots 0 (channel 1) and ts 16 (channel 17), the RBCS registers would be programmed as follows: RBCS1 = 01h RBCS2 = 00h RBCS3 = 01h RBCS4 = FCh Register Name: Register Description: Register Address: RBCS1, RBCS2, RBCS3, RBCS4 Receive Blank Channel Select Registers 0C0h, 0C1h, 0C2h, 0C3h (LSB) CH1 CH9 CH17 CH25 (MSB) CH8 CH16 CH24 CH32 CH7 CH15 CH23 CH31 CH6 CH14 CH22 CH30 CH5 CH13 CH21 CH29 CH4 CH12 CH20 CH28 CH3 CH11 CH19 CH27 CH2 CH10 CH18 CH26 RBCS1 RBCS2 RBCS3 RBCS4 Bits 0 to 7 / Receive Blank Channel Select for Channels 1 to 32 (RBCS1 to 32) 0 = do not ignore this channel (send to RSER) 1 = ignore this E1 channel (do not send to RSER) Note that when two or more sequential channels are chosen to be ignored, the receive slip zone select bit should be set to zero. If the ignore channels are distributed (such as 1, 5, 9, 13, 17, 21, 25, 29), then the RSZS bit can be set to one, which may provide a lower occurrence of slips in certain applications. 191 DS26401 Octal T1/E1/J1 Framer 10.13.2 Additional E1 Receive Elastic Store Information If the receive side elastic store is enabled, then the user must provide either a 1.544MHz or 2.048MHz clock at the RSYSCLK pin. For higher rate system clock applications, see the Interleave Bus Option section. The user has the option of either providing a frame/multiframe sync at the RSYNC pin or having the RSYNC pin provide a pulse on frame/multiframe boundaries. If Signaling Reinsertion is enabled, signaling data in TS16 is re-aligned to the multiframe sync input on RSYNC. Otherwise, a multiframe sync input on RSYNC is treated as a simple frame boundary by the elastic store. The framer will always indicate frame boundaries on the network side of the elastic store via the RFSYNC output whether the elastic store is enabled or not. Multiframe boundaries will always be indicated via the RMSYNC output. If the elastic store is enabled, then RMSYNC will output the multiframe boundary on the backplane side of the elastic store. When the device is receiving E1 and the backplane is enabled for 1.544MHz operation, the RMSYNC signal will output the E1 multiframe boundaries as delayed through the elastic store. 10.13.2.1 Elastic Stores Initialization There are two elastic store initializations that may be used to improve performance in certain applications, Elastic Store Reset and Elastic Store Align. Both of these involve the manipulation of the elastic store's read and write pointers and are useful primarily in synchronous applications (RSYSCLK/TSYSCLK are locked to RCLK/TCLK, respectively). The elastic store reset is used to minimize the delay through the elastic store. The elastic store align bit is used to 'center' the read/write pointers to the extent possible. Elastic Store Delay After Initialization INITIALIZATION Receive Elastic Store Reset Transmit Elastic Store Reset Receive Elastic Store Align Transmit Elastic Store Align N = 9 for RSZS = 0 N = 2 for RSZS = 1 REGISTER BIT RESCR.2 TESCR.2 RESCR.3 TESCR.3 DELAY N bytes < Delay < 1 Frame + N bytes N bytes < Delay < 1 Frame + N bytes 1/2 Frame < Delay < 1 1/2 Frames 1/2 Frame < Delay < 1 1/2 Frames 10.13.2.2 Minimum Delay Mode Elastic store minimum delay mode may be used when the elastic store's system clock is locked to its network clock (i.e., RCLK locked to RSYSCLK for the receive side and TCLK locked to TSYSCLK for the transmit side). RESCR.1 enable the receive elastic store minimum delay mode. When enabled the elastic stores will be forced to a maximum depth of 32 bits instead of the normal two-frame depth. This feature is useful primarily in T1 applications that interface to a 2.048MHz bus. Certain restrictions apply when minimum delay mode is used. In addition to the restriction mentioned above, RSYNC must be configured as an output when the receive elastic store is in minimum delay mode and TSYNC must be configured as an output when transmit minimum delay mode is enabled. In a typical application RSYSCLK and TSYSCLK are locked to RCLK, and RSYNC (frame output mode) is connected to TSSYNC (frame input mode). All of the slip contention logic in the framer is disabled (since slips cannot occur). On power-up after the RSYSCLK and TSYSCLK signals have locked to their respective network clock signals, the elastic store reset bit (RESCR.2) should be toggled from a zero to a one to ensure proper operation. 192 DS26401 Octal T1/E1/J1 Framer 10.14 Fractional E1 Support (Gapped Clock Mode) The DS26401 can be programmed to output gapped clocks for selected channels in the receive and transmit paths to simplify connections into a USART or LAPD controller in Fractional T1/E1 or ISDN-PRI applications. When the gapped clock feature is enabled, a gated clock is output on the RCHCLK signal. The channel selection is controlled via the receive-gapped-clock channel-select registers (RGCCS1-RGCCS4). The receive path is enabled for gapped clock mode with the RGCLKEN bit (RESCR.6). Both 56kbps and 64kbps channel formats are supported as determined by RESCR.7. When 56kbps mode is selected, the clock corresponding to the Data/Control bit in the channel is omitted (only the seven most significant bits of the channel have clocks). Register Name: Register Description: Register Address: RGCCS1, RGCCS2, RGCCS3, RGCCS4 Receive Gapped Clock Channel Select Registers 0CCh, 0CDh, 0CEh, 0CFh [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8] (LSB) CH1 CH9 CH17 CH25 (MSB) CH8 CH16 CH24 CH32 CH7 CH15 CH23 CH31 CH6 CH14 CH22 CH30 CH5 CH13 CH21 CH29 CH4 CH12 CH20 CH28 CH3 CH11 CH19 CH27 CH2 CH10 CH18 CH26 RGCCS1 RGCCS2 RGCCS3 RGCCS4 Bits 0 to 7 / Receive Channels 1 to 32 Gapped Clock Channel Select Bits (CH1 to CH32) 0 = no clock is present on RCHCLK during this channel time 1 = force a clock on RCHCLK during this channel time. The clock will be synchronous with RCLK if the elastic store is disabled, and synchronous with RSYSCLK if the elastic store is enabled. 193 DS26401 Octal T1/E1/J1 Framer 10.15 Additional Sa-Bit and Si-Bit Receive Operation (E1 Mode) When operated in the E1 mode the DS21411 receiver provides extended access to both the Sa and the Si bits. The RAF and RNAF registers will always report the data as it received in the Sa and Si bit locations. The RAF and RNAF registers are updated on align frame boundaries. The setting of the Receive Align Frame bit in Latched Status Register 2 (RLS2.0) will indicate that the contents of the RAF and RNAF have been updated. The host can use the RLS2.0 bit to know when to read the RAF and RNAF registers. The host has 250ms to retrieve the data before it is lost. Also there are eight registers (RsiAF, RSiNAF, RRA, Rsa4 to Rsa8) that report the Si and Sa bits as they are received. These registers are updated with the setting of the Receive CRC4 Multiframe bit in Latched Status Register 2 (RLS2.1). The host can use the RLS2.1 bit to know when to read these registers. The user has 2ms to retrieve the data before it is lost. Please see the register descriptions below for additional information. Register Name: Register Description: Register Address: Bit # Name Default 7 Si 0 RAF Receive Align Frame Register 064h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 0 0 5 0 0 4 1 0 3 1 0 2 0 0 1 1 0 0 1 0 Bit 0 / Frame Alignment Signal Bit (1) Bit 1 / Frame Alignment Signal Bit (1) Bit 2 / Frame Alignment Signal Bit (0) Bit 3 / Frame Alignment Signal Bit (1) Bit 4 / Frame Alignment Signal Bit (1) Bit 5 / Frame Alignment Signal Bit (0) Bit 6 / Frame Alignment Signal Bit (0) Bit 7 / International Bit (Si) 194 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 Si 0 RNAF Receive Non-Align Frame Register 065h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 1 0 5 A 0 4 Sa4 0 3 Sa5 0 2 Sa6 0 1 Sa7 0 0 Sa8 0 Bit 0 / Additional Bit 8 (Sa8) Bit 1 / Additional Bit 7 (Sa7) Bit 2 / Additional Bit 6 (Sa6) Bit 3 / Additional Bit 5 (Sa5) Bit 4 / Additional Bit 4 (Sa4) Bit 5 / Remote Alarm (A) Bit 6 / Frame Non-Alignment Signal Bit (1) Bit 7 / International Bit (Si) Register Name: Register Description: Register Address: Bit # Name Default 7 SiF14 0 RsiAF Received Si Bits of the Align Frame 066h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 SiF12 0 5 SiF10 0 4 SiF8 0 3 SiF6 0 2 SiF4 0 1 SiF2 0 0 SiF0 0 Bit 0 / Si Bit of Frame 0 (SiF0) Bit 1 / Si Bit of Frame 2 (SiF2) Bit 2 / Si Bit of Frame 4 (SiF4) Bit 3 / Si Bit of Frame 6 (SiF6) Bit 4 / Si Bit of Frame 8 (SiF8) Bit 5 / Si Bit of Frame 10 (SiF10) Bit 6 / Si Bit of Frame 12 (SiF12) Bit 7 / Si Bit of Frame 14 (SiF14) 195 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 SiF15 0 RSiNAF Received Si Bits of the Non-Align Frame 067h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 SiF13 0 5 SiF11 0 4 SiF9 0 3 SiF7 0 2 SiF5 0 1 SiF3 0 0 SiF1 0 Bit 0 / Si Bit of Frame 1 (SiF1) Bit 1 / Si Bit of Frame 3 (SiF3) Bit 2 / Si Bit of Frame 5 (SiF5) Bit 3 / Si Bit of Frame 7 (SiF7) Bit 4 / Si Bit of Frame 9 (SiF9) Bit 5 / Si Bit of Frame 11 (SiF11) Bit 6 / Si Bit of Frame 13 (SiF13) Bit 7 / Si Bit of Frame 15 (SiF15) Register Name: Register Description: Register Address: Bit # Name Default 7 RRAF15 0 RRA Received Remote Alarm 068h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 RRAF13 0 5 RRAF11 0 4 RRAF9 0 3 RRAF7 0 2 RRAF5 0 1 RRAF3 0 0 RRAF1 0 Bit 0 / Remote Alarm Bit of Frame 1 (RRAF1) Bit 1 / Remote Alarm Bit of Frame 3 (RRAF3) Bit 2 / Remote Alarm Bit of Frame 5 (RRAF5) Bit 3 / Remote Alarm Bit of Frame 7 (RRAF7) Bit 4 / Remote Alarm Bit of Frame 9 (RRAF9) Bit 5 / Remote Alarm Bit of Frame 11 (RRAF11) Bit 6 / Remote Alarm Bit of Frame 13 (RRAF13) Bit 7 / Remote Alarm Bit of Frame 15 (RRAF15) 196 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 RSa4F15 RSa4 Received Sa4 Bits 069h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 RSa4F13 5 RSa4F11 4 RSa4F9 3 RSa4F7 2 RSa4F5 1 RSa4F3 0 RSa4F1 0 0 0 0 0 0 0 0 Bit 0 / Sa4 Bit of Frame 1 (RSa4F1) Bit 1 / Sa4 Bit of Frame 3 (RSa4F3) Bit 2 / Sa4 Bit of Frame 5 (RSa4F5) Bit 3 / Sa4 Bit of Frame 7 (RSa4F7) Bit 4 / Sa4 Bit of Frame 9 (RSa4F9) Bit 5 / Sa4 Bit of Frame 11 (RSa4F11) Bit 6 / Sa4 Bit of Frame 13 (RSa4F13) Bit 7 / Sa4 Bit of Frame 15 (RSa4F15) Register Name: Register Description: Register Address: Bit # Name Default 7 RSa5F15 RSa5 Received Sa5 Bits 06Ah + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 RSa5F13 5 RSa5F11 4 RSa5F9 3 RSa5F7 2 RSa5F5 1 RSa5F3 0 RSa5F1 0 0 0 0 0 0 0 0 Bit 0 / Sa5 Bit of Frame 1 (RSa5F1) Bit 1 / Sa5 Bit of Frame 3 (RSa5F3) Bit 2 / Sa5 Bit of Frame 5 (RSa5F5) Bit 3 / Sa5 Bit of Frame 7 (RSa5F7) Bit 4 / Sa5 Bit of Frame 9 (RSa5F9) Bit 5 / Sa5 Bit of Frame 11 (RSa5F11) Bit 6 / Sa5 Bit of Frame 13 (RSa5F13) Bit 7 / Sa5 Bit of Frame 15 (RSa5F15) 197 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 RSa6F15 RSa6 Received Sa6 Bits 06Bh + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 RSa6F13 5 RSa6F11 4 RSa6F9 3 RSa6F7 2 RSa6F5 1 RSa6F3 0 RSa6F1 0 0 0 0 0 0 0 0 Bit 0 / Sa6 Bit of Frame 1 (RSa6F1) Bit 1 / Sa6 Bit of Frame 3 (RSa6F3) Bit 2 / Sa6 Bit of Frame 5 (RSa6F5) Bit 3 / Sa6 Bit of Frame 7 (RSa6F7) Bit 4 / Sa6 Bit of Frame 9 (RSa6F9) Bit 5 / Sa6 Bit of Frame 11 (RSa6F11) Bit 6 / Sa6 Bit of Frame 13 (RSa6F13) Bit 7 / Sa6 Bit of Frame 15 (RSa6F15) Register Name: Register Description: Register Address: Bit # Name Default 7 RSa7F15 RSa7 Received Sa7 Bits 06Ch + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 RSa7F13 5 RSa7F11 4 RSa7F9 3 RSa7F7 2 RSa7F5 1 RSa7F3 0 RSa7F1 0 0 0 0 0 0 0 0 Bit 0 / Sa7 Bit of Frame 1 (RSa7F1) Bit 1 / Sa7 Bit of Frame 3 (RSa7F3) Bit 2 / Sa7 Bit of Frame 5 (RSa7F5) Bit 3 / Sa7 Bit of Frame 7 (RSa7F7) Bit 4 / Sa7 Bit of Frame 9 (RSa7F9) Bit 5 / Sa7 Bit of Frame 11 (RSa7F11) Bit 6 / Sa7 Bit of Frame 13 (RSa7F13) Bit 7 / Sa7 Bit of Frame 15 (RSa4F15) 198 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 RSa8F15 RSa8 Received Sa8 Bits 06Dh + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 RSa8F13 5 RSa8F11 4 RSa8F9 3 RSa8F7 2 RSa8F5 1 RSa8F3 0 RSa8F1 0 0 0 0 0 0 0 0 Bit 0 / Sa8 Bit of Frame 1 (RSa8F1) Bit 1 / Sa8 Bit of Frame 3 (RSa8F3) Bit 2 / Sa8 Bit of Frame 5 (RSa8F5) Bit 3 / Sa8 Bit of Frame 7 (RSa8F7) Bit 4 / Sa8 Bit of Frame 9 (RSa8F9) Bit 5 / Sa8 Bit of Frame 11 (RSa8F11) Bit 6 / Sa8 Bit of Frame 13 (RSa8F13) Bit 7 / Sa8 Bit of Frame 15 (RSa8F15) 199 DS26401 Octal T1/E1/J1 Framer 10.16 Receive HDLC Controller Each framer port has an HDLC controller with 64-byte FIFOs. The HDLC controllers automatically generate and detect flags, generate and check the CRC checksum, generate and detect abort sequences, stuff and destuff zeros, and byte align to the data stream. Register Name: Register Description: Register Address: Bit # Name Default 7 RCRCD 0 RHC Receive HDLC Control Register 010h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 RHR 0 5 RHMS 0 4 RHCS4 0 3 RHCS3 0 2 RHCS2 0 1 RHCS1 0 0 RHCS0 0 Bit 0 to Bit 4 / Receive HDLC Channel Select (RHCSx). These bits determine which DS0 is mapped to the HDLC controller when enabled with RHMS = 0. RHCS0 to RHCS4 = all 0s selects channel 1, RHCS0 to RHCS4 = all 1s selects channel 32 (E1). Bit 5 / Receive HDLC Mapping Select (RHMS) 0 = Receive HDLC assigned to channels 1 = Receive HDLC assigned to FDL (T1 mode), Sa Bits (E1 mode) Bit 6 / Receive HDLC Reset (RHR). Will reset the receive HDLC controller and flush the receive FIFO. Must be cleared and set again for a subsequent reset. 0 = Normal operation 1 = Reset receive HDLC controller and flush the receive FIFO Bit 7 / Receive CRC16 Display (RCRCD) 0 = Do not write received CRC16 code to FIFO 1= Write received CRC16 code to FIFO after last octet of packet Register Name: Register Description: Register Address: Bit # Name Default 7 BSE8 0 RHBSE Receive HDLC Bit Suppress Register 011h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 BSE7 0 5 BSE6 0 4 BSE5 0 3 BSE4 0 2 BSE3 0 1 BSE2 0 0 BSE1 0 Bit 0 / Receive Channel Bit 1 Suppress/Sa8 Bit Suppress (BSE1). LSB of the channel. Set to one to stop this bit from being used. Bit 1 / Receive Channel Bit 2 Suppress/Sa7 Bit Suppress (BSE2). Set to one to stop this bit from being used Bit 2 / Receive Channel Bit 3 Suppress/Sa6 Bit Suppress (BSE3). Set to one to stop this bit from being used Bit 3 / Receive Channel Bit 4 Suppress/Sa5 Bit Suppress (BSE4). Set to one to stop this bit from being used Bit 4 / Receive Channel Bit 5 Suppress/Sa4 Bit Suppress (BSE5). Set to one to stop this bit from being used Bit 5 / Receive Channel Bit 6 Suppress (BSE6). Set to one to stop this bit from being used. Bit 6 / Receive Channel Bit 7 Suppress (BSE7). Set to one to stop this bit from being used. Bit 7 / Receive Channel Bit 8 Suppress (BSE8). MSB of the channel. Set to one to stop this bit from being used. 200 DS26401 Octal T1/E1/J1 Framer 10.16.1 HDLC FIFO Control Control of the receive FIFO is accomplished via the Receive HDLC FIFO Control (RHFC). The FIFO Control register sets the watermarks for the receive FIFO. When the receive FIFO fills above the high watermark, the RHWM bit (RRTS5.1) will be set. RHWM is a real-time bit and will remain set as long as the receive FIFO's write pointer is above the watermark. If enabled, this condition can also cause an interrupt via the INT pin. Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 RHFC Receive HDLC FIFO Control Register 087h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 -- 0 1 RFHWM1 0 0 RFHWM0 0 Bits 0 to 1 / Receive FIFO High Watermark Select (RFHWM0 to RFHWM1) RFHWM1 0 0 1 RFHWM0 0 1 0 Receive FIFO Watermark (bytes) 4 16 32 1 1 48 Bits 2 to 7/ Unused. Must be set = 0 for proper operation. 201 DS26401 Octal T1/E1/J1 Framer 10.16.2 Receive Packet Bytes Available The lower 6 bits of the Receive Packet Bytes Available register indicates the number of bytes (0 through 64) that can be read from the receive FIFO. The value indicated by this register informs the host as to how many bytes can be read from the receive FIFO without going past the end of a message. This value will refer to one of four possibilities, the first part of a packet, the continuation of a packet, the last part of a packet, or a complete packet. After reading the number of bytes indicated by this register the host then checks the HDLC Status register for detailed message status. If the value in the RHPBA register refers to the beginning portion of a message or continuation of a message then the MSB of the RHPBA register will return a value of 1. This indicates that the host may safely read the number of bytes returned by the lower 6 bits of the RHPBA register but there is no need to check the information register since the packet has not yet terminated (successfully or otherwise). Register Name: Register Description: Register Address: Bit # Name Default 7 MS 0 RHPBA Receive HDLC Packet Bytes Available Register 0B5h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 RPBA6 0 5 RPBA5 0 4 RPBA4 0 3 RPBA3 0 2 RPBA2 0 1 RPBA1 0 0 RPBA0 0 Bits 0 to 6 / Receive FIFO Packet Bytes Available Count (RPBA0 to RPBA6). RPBA0 is the LSB. Bit 7 / Message Status (MS) 0 = Bytes indicated by RPBA0 through RPBA6 are the end of a message. Host must check the HDLC Status register for details. 1 = Bytes indicated by RPBA0 through RPBA6 are the beginning or continuation of a message. The host does not need to check the HDLC Status. 202 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 RHD7 0 RHF Receive HDLC FIFO Register 0B6h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 RHD6 0 5 RHD5 0 4 RHD4 0 3 RHD3 0 2 RHD2 0 1 RHD1 0 0 RHD0 0 Bit 0 / Receive HDLC Data Bit 0 (RHD0). LSB of a HDLC packet data byte. Bit 1 / Receive HDLC Data Bit 1 (RHD1) Bit 2 / Receive HDLC Data Bit 2 (RHD2) Bit 3 / Receive HDLC Data Bit 3 (RHD3) Bit 4 / Receive HDLC Data Bit 4 (RHD4) Bit 5 / Receive HDLC Data Bit 5 (RHD5) Bit 6 / Receive HDLC Data Bit 6 (RHD6) Bit 7 / Receive HDLC Data Bit 7 (RHD7). MSB of a HDLC packet data byte. 203 DS26401 Octal T1/E1/J1 Framer 10.16.3 HDLC Status and Information RRTS5 and RLS5 provide status information for the receive HDLC controller. When a particular event has occurred (or is occurring), the appropriate bit in one of these registers will be set to a one. With the latched bits, when an event occurs and a bit is set to a one, it will remain set until the user reads that bit. The bit will be cleared when it is read and it will not be set again until the event has occurred again. The real-time bits report the current instantaneous conditions that are occurring and the history of these bits is not latched. Like the other latched status registers, the user will follow a read of the status bit with a write. The byte written to the register will inform the device which of the latched bits the user wishes to clear (the real time bits are not affected by writing to the status register). The user will write a byte to one of these registers, with a one in the bit positions he or she wishes to clear and a zero in the bit positions he or she does not wish to clear. The HDLC status register RLS5 has the ability to initiate a hardware interrupt via the INT output signal. Each of the events in this register can be either masked or unmasked from the interrupt pin via the receive HDLC Interrupt Mask Register (RIM5). Interrupts will force the INT signal low when the event occurs. The INT pin will be allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the interrupt to occur. Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 RRTS5 Receive Real-Time Status 5 (HDLC) 0B4h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 PS2 0 5 PS1 0 4 PS0 0 3 --0 2 -- 0 1 RHWM 0 0 RNE 0 All bits in this register are real-time. Bit 0 / Receive FIFO Not Empty Condition (RNE). Set when the receive 64-byte FIFO has at least one byte available for a read. This is a real-time bit. Bit 1 / Receive FIFO Above High Watermark Condition (RHWM). Set when the receive 64-byte FIFO fills beyond the high watermark as defined by the Receive HDLC FIFO Control Register (RHFC). This is a real-time bit. Bits 2, 3, 7 / Unused Bits 4 to 6 / Receive Packet Status (PS0 to PS2). These are real-time bits indicating the status as of the last read of the receive FIFO. PS2 0 0 0 0 1 PS1 0 0 1 1 0 PS0 0 1 0 1 0 PACKET STATUS In Progress: End of message has not yet been reached. Packet OK: Packet ended with correct CRC codeword. CRC Error: A closing flag was detected, preceded by a corrupt CRC codeword. Abort: Packet ended because an abort signal was detected (7 or more ones in a row). Overrun: HDLC controller terminated reception of packet because receive FIFO is full. 204 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 RLS5 Receive Latched Status Register 5 (HDLC) 094h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 ROVR 0 4 RHOBT 0 3 RPE 0 2 RPS 0 1 RHWMS 0 0 RNES 0 Bit 0 / Receive FIFO Not Empty Set Event (RNES). Set when the receive FIFO has transitioned from `empty' to `not-empty' (at least one byte has been put into the FIFO). Rising edge detect of RNE. Bit 1 / Receive FIFO Above High Watermark Set Event (RHWMS). Set when the receive 64-byte FIFO crosses the high watermark as defined by the Receive HDLC FIFO Control Register (RHFC). Rising edge detect of RHWM. Bit 2 / Receive Packet Start Event (RPS). Set when the HDLC controller detects an opening byte. This is a latched bit and will be cleared when read. Bit 3 / Receive Packet End Event (RPE). Set when the HDLC controller detects either the finish of a valid message (i.e., CRC check complete) or when the controller has experienced a message fault such as a CRC checking error, or an overrun condition, or an abort has been seen. This is a latched bit and will be cleared when read. Bit 4 / Receive HDLC Opening Byte Event (RHOBT). Set when the next byte available in the receive FIFO is the first byte of a message. Bit 5 / Receive FIFO Overrun (ROVR). Set when the receive HDLC controller has terminated packet reception because the FIFO buffer is full. Bits 6, 7 / Unused 205 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 RIM5 Receive Interrupt Mask 5 (HDLC) 0A4h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 ROVR 0 4 RHOBT 0 3 RPE 0 2 RPS 0 1 RHWMS 0 0 RNES 0 Bit 0 / Receive FIFO Not Empty Set Event (RNES). 0 = interrupt masked 1 = interrupt enabled Bit 1 / Receive FIFO Above High Watermark Set Event (RHWMS) 0 = interrupt masked 1 = interrupt enabled Bit 2 / Receive Packet Start Event (RPS) 0 = interrupt masked 1 = interrupt enabled Bit 3 / Receive Packet End Event (RPE) 0 = interrupt masked 1 = interrupt enabled Bit 4 / Receive HDLC Opening Byte Event (RHOBT) 0 = interrupt masked 1 = interrupt enabled Bit 5 / Receive FIFO Overrun (ROVR) 0 = interrupt masked 1 = interrupt enabled Bits 6, 7 / Unused. Must be set = 0 for proper operation. 206 DS26401 Octal T1/E1/J1 Framer HDLC Receive Example The HDLC status registers in the DS26401 allow for flexible software interface to meet the user's preferences. When receiving HDLC messages, the host can chose to be interrupt driven, or to poll to desired status registers, or a combination of polling and interrupt processes may be used. An example routine for using the DS26401 HDLC receiver is given in Figure 10-3. Figure 10-3. Receive HDLC Example Configure Receive HDLC Controller (RHC, RHBSE, RHFC) Reset Receive HDLC Controller (RHC.6) Start New Message Buffer Enable Interrupts RPE and RHWM Interrupt? NO No Action Required Work Another Process YES Read Register RHPBA Read N Bytes From Rx HDLC FIFO (RHF) N = RHPBA[5..0] NO MS = 0? (MS = RHPBA[7]) YES Read RRTS5 for Packet Status (PS2..0) Take appropriate action 207 DS26401 Octal T1/E1/J1 Framer 10.17 Interleaved PCM Bus Operation (IBO) In many architectures, the PCM outputs of individual framers are combined into higher speed PCM buses to simplify transport across the system backplane. The DS26401 can be configured to allow PCM data to be multiplexed into higher speed buses eliminating external hardware, saving board space and cost. The DS26401 can be configured for channel or frame interleave. The interleaved PCM bus option (IBO) supports three bus speeds. The 4.096MHz bus speed allows two PCM data streams to share a common bus. The 8.192MHz bus speed allows four PCM data streams to share a common bus. The 16.384MHz bus speed allows 8 PCM data streams to share a common bus. The receive elastic stores of each transceiver must be enabled. Via the IBO register the user can configure each framer for a specific bus position. For all IBO bus configurations each framer is assigned an exclusive position in the high speed PCM bus. The 8kHz frame sync can be generated from the system backplane or from the first device on the bus. All other devices on the bus must have their frame syncs configured as inputs. Relative to this common frame sync, the devices will await their turn to drive or sample the bus according to the settings of the DA0, DA1 and DA2 bits of the RIBOC register. 10.17.1 Channel Interleave In channel interleave mode data is output to the PCM Data Out bus one channel at a time from each of the connected DS26401s until all channels of frame n from each framer has been placed on the bus. This mode can be used even when the DS26401s are operating asynchronous to each other. The elastic stores will manage slip conditions. The DS26401 provides an active high signal (RIBO_OE) during bus active times. RIBO_OE can be used for bus multiplexer or tri-state buffer control. 10.17.2 Frame Interleave In frame interleave mode data is output to the PCM Data Out bus one frame at a time from each of the framers. This mode is used only when all connected DS26401s are operating in a synchronous fashion (all inbound T1 or E1 lines are synchronous) and are synchronous with the system clock (system clock derived from T1 or E1 line). In this mode, slip conditions are not allowed. 208 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 RIBOC Receive Interleave Bus Operation Control Register 084h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 IBS1 0 5 IBS0 0 4 IBOSEL 0 3 IBOEN 0 2 DA2 0 1 DA1 0 0 DA0 0 Bits 0 to 2 / Device Assignment Bits (DA0 to DA2) DA2 0 0 0 0 1 1 1 1 DA1 0 0 1 1 0 0 1 1 DA0 0 1 0 1 0 1 0 1 Device Position 1st Device on bus 2nd Device on bus 3rd Device on bus 4th Device on bus 5th Device on bus 6th Device on bus 7th Device on bus 8th Device on bus Bit 3 / Interleave Bus Operation Enable (IBOEN) 0 = Interleave Bus Operation disabled. 1 = Interleave Bus Operation enabled. Bit 4 / Interleave Bus Operation Select (IBOSEL). This bit selects channel or frame interleave mode. 0 = Channel Interleave 1 = Frame Interleave Bits 5, 6 / IBO Bus Size bit 1 (IBS0 to IBS1). Indicates how many devices on the bus. IBS1 0 0 1 1 IBS0 0 1 0 1 Bus Size 2 Devices on bus (4.096MHz) 4 Devices on bus (8.192MHz) 8 Devices on bus (16.384MHz) Reserved for future use Bit 7 / Unused. Must be set = 0 for proper operation. 209 DS26401 Octal T1/E1/J1 Framer 10.18 Interfacing the E1 Rx Framer to the BERT Data from the DS26401 receive framer can be ported to the on-chip BERT by using the registers described below. Any single DS0 or combination of DS0s can be extracted from the data stream up to the entire T1 payload as controlled by the RBCS registers. Note that one BERT resource is shared between all 8 framers. Therefore, the RBEN bit should be set for only one framer at a time. If multiple framers have the RBEN bit set, the lower number framer will be assigned the resource. Details concerning the on-chip BERT can be found in Section 12. Register Name: Register Description: Register Address: Bit # Name Default 7 -- RBICR Receive BERT Interface Control Register 08Ah + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 5 -- 4 -- 3 -- 0 0 0 0 0 2 RBDC 0 1 -- 0 0 RBEN 0 Bit 0 / Receive BERT Enable (RBEN) 0 = Receive BERT is not assigned to this framer 1 = Receive BERT is assigned to this framer Bit 1 / Unused. Must be set = 0 for proper operation. Bit 2 / Receive BERT Direction Control (RBDC) 0 = Receive Path: The BERT receives data from the network side via RPOS and RNEG. 1 = Backplane: The BERT receives data from the system backplane via the TSER pin. Bits 2 to 7 / Unused. Must be set = 0 for proper operation. 210 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: RBCS1, RBCS2, RBCS3, RBCS4 Receive BERT Channel Select Registers 0D4h, 0D5h, 0D6h, 0D7h [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8] Setting any of the CH1 through CH32 bits in the RBCS1 through RBCS4 registers will map data from those channels to the on-board BERT. RBEN must be set to one for these registers to have effect. Multiple, or all channels may be selected simultaneously. These registers work with the receive-side framer only. (MSB) CH8 CH16 CH24 CH32 (LSB) CH1 CH9 CH17 CH25 CH7 CH15 CH23 CH31 CH6 CH14 CH22 CH30 CH5 CH13 CH21 CH29 CH4 CH12 CH20 CH28 CH3 CH11 CH19 CH27 CH2 CH10 CH18 CH26 RBCS1 RBCS2 RBCS3 RBCS4 Register Name: Register Description: Register Address: Bit # Name Default 7 BSE8 0 RBBS Receive BERT Bit Suppress Register 08Bh 6 BSE7 0 5 BSE6 0 4 BSE5 0 3 BSE4 0 2 BSE3 0 1 BSE2 0 0 BSE1 0 Bit 0 / Receive Channel Bit 1 Suppress (BSE1). LSB of the channel. Set to one to stop this bit from being used. Bit 1 / Receive Channel Bit 2 Suppress (BSE2). Set to one to stop this bit from being used. Bit 2 / Receive Channel Bit 3 Suppress (BSE3). Set to one to stop this bit from being used. Bit 3 / Receive Channel Bit 4 Suppress (BSE4). Set to one to stop this bit from being used. Bit 4 / Receive Channel Bit 5 Suppress (BSE5). Set to one to stop this bit from being used. Bit 5 / Receive Channel Bit 6 Suppress (BSE6). Set to one to stop this bit from being used. Bit 6 / Receive Channel Bit 7 Suppress (BSE7). Set to one to stop this bit from being used. Bit 7 / Receive Channel Bit 8 Suppress (BSE8). MSB of the channel. Set to one to stop this bit from being used. 211 DS26401 Octal T1/E1/J1 Framer 11. E1 TRANSMIT 11.1 E1 Transmit Register Map ADDRESS 100 101 102 103 104 105 106 107 108 109 10A 10B 10C 10D 10E 10F 110 111 112 113 114 115 116 117 118 119 11A 11B 11C 11D 11E 11F 120 121 122 123 124 125 126 127 128 129 12A 12B 12C 12D 12E 12F 130 131 132 133 134 135 136 137 TYPE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- R/W R/W -- R/W R/W -- -- -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W FUNCTION Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Tx HDLC Control 1 Tx HDLC Bit Suppress Unused Tx HDLC Control 2 Tx Sa Bit Control Register Unused Unused Unused Tx Software Signaling Insertion Enable 1 Tx Software Signaling Insertion Enable 2 Tx Software Signaling Insertion Enable 3 Tx Software Signaling Insertion Enable 4 Tx Test Register 1 Tx Test Register 2 Tx Test Register 3 Tx Test Register 4 Tx Idle Definition 1 Tx Idle Definition 2 Tx Idle Definition 3 Tx Idle Definition 4 Tx Idle Definition 5 Tx Idle Definition 6 Tx Idle Definition 7 Tx Idle Definition 8 Tx Idle Definition 9 Tx Idle Definition 10 Tx Idle Definition 11 Tx Idle Definition 12 Tx Idle Definition 13 Tx Idle Definition 14 Tx Idle Definition 15 Tx Idle Definition 16 Tx Idle Definition 17 Tx Idle Definition 18 Tx Idle Definition 19 Tx Idle Definition 20 Tx Idle Definition 21 Tx Idle Definition 22 Tx Idle Definition 23 Tx Idle Definition 24 NAME -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- THC1 THBSE -- THC2 TSACR -- -- -- SSIE1 SSIE2 SSIE3 SSIE4 TTEST1 TTEST2 TTEST3 TTEST4 TIDR1 TIDR2 TIDR3 TIDR4 TIDR5 TIDR6 TIDR7 TIDR8 TIDR9 TIDR10 TIDR11 TIDR12 TIDR13 TIDR14 TIDR15 TIDR16 TIDR17 TIDR18 TIDR19 TIDR20 TIDR21 TIDR22 TIDR23 TIDR24 PAGE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 248 249 -- 249 246 -- -- -- 121 121 121 121 -- -- -- -- 233 233 233 233 233 233 233 233 233 233 233 233 233 233 233 233 233 233 233 233 233 233 233 233 212 DS26401 Octal T1/E1/J1 Framer ADDRESS 138 139 13A 13B 13C 13D 13E 13F 140 141 142 143 144 145 146 147 148 149 14A 14B 14C 14D 14E 14F 150 151 152 153 154 155 156 157 158 159 15A 15B 15C 15D 15E 15F 160 161 162 163 164 165 166 167 168 169 16A 16B 16C 16D 16E 16F 170 171 172 173 174 TYPE R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W -- -- -- -- -- -- -- FUNCTION Tx Idle Definition 25 Tx Idle Definition 26 Tx Idle Definition 27 Tx Idle Definition 28 Tx Idle Definition 29 Tx Idle Definition 30 Tx Idle Definition 31 Tx Idle Definition 32 Tx Signaling 1 Tx Signaling 2 Tx Signaling 3 Tx Signaling 4 Tx Signaling 5 Tx Signaling 6 Tx Signaling 7 Tx Signaling 8 Tx Signaling 9 Tx Signaling 10 Tx Signaling 11 Tx Signaling 12 Tx Signaling 13 Tx Signaling 14 Tx Signaling 15 Tx Signaling 16 Tx Channel Idle Code Enable 1 Tx Channel Idle Code Enable 2 Tx Channel Idle Code Enable 3 Tx Channel Idle Code Enable 4 Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Tx Align Frame Tx Non-Align Frame Tx Si bits for Align Frame Tx Si bits for Non-Align Frame Tx Remote Alarm Tx Sa4 Bits Tx Sa5 Bits Tx Sa6 Bits Tx Sa7 Bits Tx Sa8 Bits Unused Unused Unused Unused Unused Unused Unused NAME TIDR25 TIDR26 TIDR27 TIDR28 TIDR29 TIDR30 TIDR31 TIDR32 TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS12 TS13 TS14 TS15 TS16 TCICE1 TCICE2 TCICE3 TCICE4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TAF TNAF TSiAF TSiNAF TRA TSa4 TSa5 TSa6 TSa7 TSa8 -- -- -- -- -- -- -- PAGE 233 233 233 233 233 233 233 233 231 231 231 231 231 231 231 231 231 231 231 231 231 231 231 231 233 233 233 233 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 241 241 242 242 243 243 244 244 245 245 -- -- -- -- -- -- -- 213 DS26401 Octal T1/E1/J1 Framer ADDRESS 175 176 177 178 179 17A 17B 17C 17D 17E 17F 180 181 182 183 184 185 186 187 188 189 18A 18B 18C 18D 18E 18F 190 191 192 193 194 195 196 197 198 199 19A 19B 19C 19D 19E 19F 1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 1A9 1AA 1AB 1AC 1AD 1AE 1AF 1B0 1B1 TYPE -- -- -- -- -- -- -- -- -- -- -- R/W R/W R/W R/W R/W R/W -- R/W R/W R/W R/W R/W -- -- R/W R/W R/W R/W R/W -- -- -- -- -- -- -- -- -- -- -- -- R/W R/W R/W R/W -- -- -- -- -- -- -- -- -- -- -- -- -- -- R FUNCTION Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Tx Master Mode Tx Control 1 Tx Control 2 Tx Control 3 Tx I/O Configuration Tx Elastic Store Control Unused Tx HDLC FIFO Control Tx Interleave Bus Op Control Tx DS0 Monitor Select Tx BERT Interface Control Tx BERT Bit Suppress En Unused Unused Tx Synchronizer Control Tx Test Register 5 Tx Latched Status 1 Tx Latched Status 2 (HDLC) Tx Latched Status 3 (SYNC) Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Tx Interrupt Information Register Tx Interrupt Mask Register 1 Tx Interrupt Mask Register 2 (HDLC) Tx Interrupt Mask Register 3 (SYNC) Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Tx Real-Time Status Register 2 (HDLC) NAME -- -- -- -- -- -- -- -- -- -- -- TMMR TCR1 TCR2 TCR3 TIOCR TESCR -- THFC TIBOC TDS0SEL TBICR TBBS -- -- TSYNCC TTEST5 TLS1 TLS2 TLS3 -- -- -- -- -- -- -- -- -- -- -- -- TIIR TIM1 TIM2 TIM3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- TRTS2 PAGE -- -- -- -- -- -- -- -- -- -- -- 217 219 220 222 114 237 -- 250 257 229 258 259 -- -- 260 -- 226 252 261 -- -- -- -- -- -- -- -- -- -- -- -- 218 227 253 261 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 251 214 DS26401 Octal T1/E1/J1 Framer ADDRESS 1B2 1B3 1B4 1B5 1B6 1B7 1B8 1B9 1BA 1BB 1BC 1BD 1BE 1BF 1C0 1C1 1C2 1C3 1C4 1C5 1C6 1C7 1C8 1C9 1CA 1CB 1CC 1CD 1CE 1CF 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9 1DA 1DB 1DC 1DD 1DE 1DF 1E0-1FF TYPE -- R W -- -- -- -- -- -- R -- -- -- -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W -- -- -- -- -- -- -- -- -- FUNCTION Unused Tx HDLC FIFO Buffer Available Tx HDLC FIFO Unused Unused Unused Unused Unused Unused Tx DS0 Monitor Unused Unused Unused Unused Tx Blank Channel Select 1 Tx Blank Channel Select 2 Tx Blank Channel Select 3 Tx Blank Channel Select 4 Tx Channel Blocking 1 Tx Channel Blocking 2 Tx Channel Blocking 3 Tx Channel Blocking 4 Tx Hardware Signaling Channel Select 1 Tx Hardware Signaling Channel Select 2 Tx Hardware Signaling Channel Select 3 Tx Hardware Signaling Channel Select 4 Tx Gapped Clock Channel Select 1 Tx Gapped Clock Channel Select 2 Tx Gapped Clock Channel Select 3 Tx Gapped Clock Channel Select 4 Per-Channel Loopback Enable 1 Per-Channel Loopback Enable 2 Per-Channel Loopback Enable 3 Per-Channel Loopback Enable 4 Tx BERT Channel Select 1 Tx BERT Channel Select 2 Tx BERT Channel Select 3 Tx BERT Channel Select 4 Unused Unused Unused Unused Unused Unused Unused Unused Unused NAME -- TFBA THF -- -- -- -- -- -- TDS0M -- -- -- -- TBCS1 TBCS2 TBCS3 TBCS4 TCBR1 TCBR2 TCBR3 TCBR4 THSCS1 THSCS2 THSCS3 THSCS4 TGCCS1 TGCCS2 TGCCS3 TGCCS4 PCL1 PCL2 PCL3 PCL4 TBCS1 TBCS2 TBCS3 TBCS4 -- -- -- -- -- -- -- -- -- PAGE -- 254 254 -- -- -- -- -- -- 229 -- -- -- -- 259 259 259 259 234 234 234 234 232 232 232 232 239 239 239 239 118 118 118 -- 259 259 259 259 -- -- -- -- -- -- -- -- -- Note: The register addresses are 9 bits wide, but are shown here in hexadecimal. Addresses with the MSB clear (0xxH) are used for the DS26401 receiver; addresses with the MSB set (1xxH) are used for the DS26401 transmitter. 215 DS26401 Octal T1/E1/J1 Framer 11.2 E1 Transmit Formatter Description and Operation Eight fully independent DS1/E1 transmit formatters are included within the DS26401. The formatters are designed to interface seamlessly to the line side via an external LIU. Each port can be individually programmed to transmit AMI, HDB3 (E1), or NRZ data. In E1 mode, each formatter supports FAS, CRC-4, and CAS frame formats, transmits common alarms such as AIS and RAI. Each transmitter has an HDLC controllers which can be mapped into a single time slot, or Sa4 to Sa8 bits (E1 mode) or the FDL (T1 mode) and has 64-byte FIFO buffers in both the transmit and receive paths. Host interface is simplified with status registers optimized for either interrupt driven or polled environments. In many cases, status bits are reported both real-time and latched on change-of-state with separate bits for each state change. Most latched bits can be mapped to generate an external interrupt on the INT pin. Additional details concerning the operation of the E1 formatter are included within the register descriptions within this section. 216 DS26401 Octal T1/E1/J1 Framer 11.3 Transmit Master Mode Register The Transmit Master Mode Register (TMMR) controls the initialization of the transmit side formatter. The FRM_EN bit may be left `low' if the formatter for that particular port is not going to be used, putting the circuit in a low-power (sleep) state. Register Name: Register Description: Register Address: Bit # Name Default 7 FRM_EN TMMR Transmit Master Mode Register 180h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 INIT_DONE 5 -- 4 -- 3 -- 2 -- 1 SFTRST 0 T1/E1 0 0 0 0 0 0 0 0 Bit 0 / Transmitter T1/E1 Mode Select (T1/E1). Sets operating mode for transmitter only! This bit must be written with the desired value prior to setting INIT_DONE. 0 = T1 operation 1 = E1 operation Bit 1 / Soft Reset (SFTRST). Level sensitive processor reset. Should be taken high then low to reset and initialize the internal processor. 0 = Normal Operation 1 = Hold the internal RISC in reset. This bit only affects the transmit side processor. Bits 2 to 5 / Unused. Must be set = 0 for proper operation. Bit 6 / Initialization Done (INIT_DONE). The host (user) must set this bit once he/she has written the configuration registers. The host is required to write or clear all RAM based registers (addresses 100H to 17FH) prior to setting this bit. Once INIT_DONE is set, the internal processor will check the FRM_EN bit. If enabled, the internal processor continues executing based on the initial configuration. Bit 7 / Framer Enable (FRM_EN). This bit must be written with the desired value prior to setting INIT_DONE. 0 = Framer disabled - held in low power state 1 = Framer enabled - all features active 217 DS26401 Octal T1/E1/J1 Framer 11.4 Interrupt Information Registers The Interrupt Information Registers provide an indication of which DS26401 Status Registers are generating an interrupt. When an interrupt occurs, the host can read TIIR to quickly identify which of the transmit status registers are causing the interrupt(s). These are real-time registers in that the bits will clear once the appropriate interrupt has been serviced and cleared. Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 TIIR Transmit Interrupt Information Register 19Fh + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 TLS3 0 1 TLS2 0 0 TLS1 0 218 DS26401 Octal T1/E1/J1 Framer 11.5 E1 Transmit Control Registers Register Name: Register Description: Register Address: Bit # Name Default 7 TFPT 0 TCR1 Transmit Control Register 1 181h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 T16S 0 5 TG802 0 4 TSiS 0 3 TSA1 0 2 THDB3 0 1 TAIS 0 0 TCRC4 0 Bit 0 / Transmit CRC4 Enable (TCRC4) 0 = CRC4 disabled 1 = CRC4 enabled Bit 1 / Transmit AIS (TAIS) 0 = transmit data normally 1 = transmit an unframed all-ones code at TPOS and TNEG Bit 2 / Transmit HDB3 Enable (THDB3) 0 = HDB3 disabled 1 = HDB3 enabled Bit 3 / Transmit Signaling All Ones (TSA1) 0 = normal operation 1 = force time slot 16 in every frame to all ones Bit 4 / Transmit International Bit Select (TSiS) 0 = sample Si bits at TSER pin 1 = source Si bits from TAF and TNAF registers (in this mode, TCR1.7 must be set to 0) Bit 5 / Transmit G.802 Enable (TG802) 0 = do not force TCHBLK high during bit 1 of time slot 26 1 = force TCHBLK high during bit 1 of time slot 26 Bit 6 / Transmit Time Slot 16 Data Select (T16S) 0 = time slot 16 determined by the SSIEx and THSCS registers 1 = source time slot 16 from TS1 to TS16 registers Bit 7 / Transmit Time Slot 0 Pass Through (TFPT) 0 = FAS bits/Sa bits/Remote Alarm sourced internally from the TAF and TNAF registers 1 = FAS bits/Sa bits/Remote Alarm sourced from TSER 219 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 AEBE 0 TCR2 Transmit Control Register 2 182h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 AAIS 0 5 ARA 0 4 -- 0 3 -- 0 2 -- 0 1 -- 0 0 -- 0 Bits 0 to 4 / Unused. Must be set = 0 for proper operation. Bit 5 / Automatic Remote Alarm Generation (ARA) 0 = disabled 1 = enabled Bit 6 / Automatic AIS Generation (AAIS) 0 = disabled 1 = enabled Bit 7 / Automatic E-Bit Enable (AEBE) 0 = E-bits not automatically set in the transmit direction 1 = E-bits automatically set in the transmit direction 220 DS26401 Octal T1/E1/J1 Framer 11.6 Automatic Alarm Generation The device can be programmed to automatically transmit AIS or Remote Alarm. When automatic AIS generation is enabled (TCR2.6 = 1), the device monitors the receive side framer to determine if any of the following conditions are present: loss of receive frame synchronization, AIS alarm (all one's) reception, or loss of receive carrier (or signal). If any one (or more) of the above conditions is present, then the framer forces an AIS. When automatic RAI generation is enabled (TCR2.5 = 1), the framer monitors the receive side to determine if any of the following conditions are present: loss of receive frame synchronization, AIS alarm (all ones) reception, or loss of receive carrier (or signal) or if CRC4 multiframe synchronization cannot be found within 128ms of FAS synchronization (if CRC4 is enabled). If any one (or more) of the above conditions is present, then the framer will transmit a RAI alarm. RAI generation conforms to ETS 300 011 specifications and a constant Remote Alarm will be transmitted if the DS26401 cannot find CRC4 multiframe synchronization within 400ms as per G.706. Note: It is an illegal state to have both automatic AIS generation and automatic Remote Alarm generation enabled at the same time. 221 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 ODF 0 TCR3 Transmit Control Register 3 183h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 ODM 0 5 TCSS1 0 4 TCSS0 0 3 MFRS 0 2 -- 0 1 IBPV 0 0 CRC4R 0 Bit 0 / CRC-4 Recalculate (CRC4R) 0 = transmit CRC-4 generation and insertion operates in normal mode 1 = transmit CRC-4 generation operates according to G.706 Intermediate Path Recalculation method. Bit 1 / Insert BPV (IBPV). A 0-to-1 transition on this bit will cause a single BiPolar Violation (BPV) to be inserted into the transmit data stream. Once this bit has been toggled from a 0 to a 1, the device waits for the next occurrence of three consecutive ones to insert the BPV. This bit must be cleared and set again for a subsequent error to be inserted. Bit 2 / Unused. Must be set = 0 for proper operation. Bit 3 / Multiframe Reference Select (MFRS). This bit selects the source for the transmit formatter multiframe boundary. 0 = Normal Operation. Transmit multiframe boundary is determined by 'line-side' counters referenced to TSYNC when TSYNC is an input. Free running when TSYNC is an output. 1 = Pass-Forward Operation. Tx multiframe boundary determined by 'system-side' counters referenced to TSSYNC input, which is then 'passed forward' to the line side clock domain. This mode can only be used when the transmit elastic store is enabled with a synchronous backplane (i.e., no frame slips allowed). This mode must be used to allow Tx hardware signaling insertion while the Tx elastic store is enabled. Bit 4 / Transmit Clock Source Select bit 0 (TCSS0) Bit 5 / Transmit Clock Source Select bit 1 (TCSS1) TCSS1 0 0 1 1 TCSS0 0 1 0 1 Transmit Clock Source The TCLK pin is always the source of Transmit Clock. Switch to the clock present at RCLK when the signal at the TCLK pin fails to transition after 1 channel time. For Future Use Use the signal present at RCLK as the Transmit Clock. The TCLK pin is ignored. Bit 6 / Output Data Mode (ODM) 0 = pulses at TPOS and TNEG are one full TCLK period wide 1 = pulses at TPOS and TNEG are 1/2 TCLK period wide Bit 7 / Output Data Format (ODF) 0 = bipolar data at TPOS and TNEG 1 = NRZ data at TPOS; TNEG = 0 222 DS26401 Octal T1/E1/J1 Framer 11.7 G.706 Intermediate CRC-4 Updating (E1 Mode Only) The DS26401 can implement the G.706 CRC-4 recalculation at intermediate path points. When this mode is enabled, the data stream presented at TSER will already have the FAS/NFAS, CRC multiframe alignment word and CRC-4 checksum in time slot 0. The user can modify the Sa bit positions and this change in data content will be used to modify the CRC-4 checksum. This modification however will not corrupt any error information the original CRC-4 checksum may contain. In this mode of operation, TSYNC must be configured to multiframe mode. The data at TSER must be aligned to the TSYNC signal. If TSYNC is an input then the user must assert TSYNC aligned at the beginning of the multiframe relative to TSER. If TSYNC is an output, the user must multiframe align the data presented to TSER. This mode is enabled with the TCR3.0 control bit (CRC4R). TPOSO/TNEGO INSERT NEW CRC-4 CODE EXTRACT OLD CRC-4 CODE TSER + CRC-4 CALCULATOR XOR MODIFY Sa BIT POSITIONS NEW Sa BIT DATA 223 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 TCLKINV TIOCR Transmit I/O Configuration Register 184h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 TSYNCINV 5 TSSYNCINV 4 TSCLKM 3 TSSM 2 TSIO 1 -- 0 TSM 0 0 0 0 0 0 0 0 Bit 0 / TSYNC Mode Select (TSM). Selects frame or multiframe mode for the TSYNC pin. 0 = frame mode 1 = multiframe mode Bit 1 / Unused. Must be set = 0 for proper operation. Bit 2 / TSYNC I/O Select (TSIO) 0 = TSYNC is an input 1 = TSYNC is an output Bit 3 / TSSYNC Mode Select (TSSM). Selects frame or multiframe mode for the TSSYNC pin. 0 = frame mode 1 = multiframe mode Bit 4 / TSYSCLK Mode Select (TSCLKM) 0 = if TSYSCLK is 1.544MHz 1 = if TSYSCLK is 2.048/4.096/8.192/16.384MHz or IBO enabled (see Section 9.20 for details on IBO function) Bit 5 / TSSYNC Invert (TSSYNCINV) 0 = No inversion 1 = Invert Bit 6 / TSYNC Invert (TSYNCINV) 1 = Invert Bit 7 / TCLK Invert (TCLKINV) 0 = No inversion 1 = Invert 224 DS26401 Octal T1/E1/J1 Framer 11.8 E1 Transmit Status and Information When a particular event has occurred (or is occurring), the appropriate bit in one of these registers will be set to a one. Status bits may operate in either a latched or real-time fashion. Some latched bits may be enabled to generate a hardware interrupt via the INT signal. Real-Time Bits Some status bits operate in a real-time fashion. These bits are read-only and indicate the present state of an alarm or a condition. Real-time bits will remain stable, and valid during the host read operation. The current value of the internal status signals can be read at any time from the real-time status registers without changing any the latched status register bits Latched Bits When an event or an alarm occurs and a latched bit is set to a one, it will remain set until cleared by the user. These bits typically respond on a change-of-state for an alarm, condition, or event; and operate in a read-then-write fashion. The user should read the value of the desired status bit, and then write a 1 to that particular bit location in order to clear the latched value (write a `0' to locations not to be cleared). Once the bit is cleared, it will not be set again until the event has occurred again. Mask Bits Some of the alarms and events can be either masked or unmasked from the interrupt pin via the Interrupt Mask Registers (TIMx). When unmasked, the INT signal will be forced low when the enabled event or condition occurs. The INT pin will be allowed to return high (if no other unmasked interrupts are present) when the user reads then clears (with a write) the alarm bit that caused the interrupt to occur. Note that the latched status bit and the INT pin will clear even if the alarm is still present. 225 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 TESF 0 TLS1 Transmit Latched Status Register 1 190h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 TESEM 0 5 TSLIP 0 4 -- 0 3 TAF 0 2 TMF 0 1 LOTCC 0 0 LOTC 0 All bits in this register are latched and can cause interrupts. Bit 0 / Loss of Transmit Clock Condition (LOTC). Set when the TCLK pin has not transitioned for approximately 3 clock periods. Will force the LOTC pin high if enabled. The host can clear this bit even if the condition is still present. The LOTC pin will remain high while the condition exists, even if the host has cleared the status bit. If enabled by TIM1.0, the INT pin transitions low when this bit is set, and transitions high when this bit is cleared (if no other unmasked interrupt conditions exist). Bit 1 / Loss of Transmit Clock Condition Clear (LOTCC). Set when the LOTC condition has cleared (a clock has been sensed at the TCLK pin). Bit 2 / Transmit Multiframe Event (TMF). Set every 2ms (regardless if CRC4 is enabled) on transmit multiframe boundaries. Used to alert the host that signaling data needs to be updated. Bit 3 / Transmit Align Frame Event (TAF). Set every 250ms at the beginning of align frames. Used to alert the host that the TAF and TNAF registers need to be updated. Bit 4 / Unused Bit 5 / Transmit Elastic Store Slip Occurrence Event (TSLIP). Set when the transmit elastic store has either repeated or deleted a frame. Bit 6 / Transmit Elastic Store Empty Event (TESEM). Set when the transmit elastic store buffer empties and a frame is repeated. Bit 7 / Transmit Elastic Store Full Event (TESF). Set when the transmit elastic store buffer fills and a frame is deleted. 226 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 TESF 0 TIM1 Transmit Interrupt Mask Register 1 1A0h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 TESEM 0 5 TSLIP 0 4 -- 0 3 TAF 0 2 TMF 0 1 LOTCC 0 0 LOTC 0 Bit 0 / Loss of Transmit Clock Condition (LOTC) 0 = interrupt masked 1 = interrupt enabled Bit 1 / Loss of Transmit Clock Clear Condition (LOTCC) 0 = interrupt masked 1 = interrupt enabled Bit 2 / Transmit Multiframe Event (TMF) 0 = interrupt masked 1 = interrupt enabled Bit 3 / Bit 3 / Transmit Align Frame Event (TAF) 0 = interrupt masked 1 = interrupt enabled Bit 4 / Unused. Must be set = 0 for proper operation. Bit 5 / Transmit Elastic Store Slip Occurrence Event (TSLIP) 0 = interrupt masked 1 = interrupt enabled Bit 6 / Transmit Elastic Store Empty Event (TESEM) 0 = interrupt masked 1 = interrupt enabled Bit 7 / Transmit Elastic Store Full Event (TESF) 0 = interrupt masked 1 = interrupt enabled 227 DS26401 Octal T1/E1/J1 Framer 11.9 Per-Channel Loopback The Per-Channel Loopback Registers (PCLRs) determine which channels (if any) from the backplane should be replaced with the data from the receive side or in other words, off of the T1 or E1 line. If this loopback is enabled, then transmit and receive clocks and frame syncs must be synchronized. One method to accomplish this would be to tie RCLK to TCLK and RFSYNC to TSYNC. There are no restrictions on which channels can be looped back or on how many channels can be looped back. Each of the bit position in the Per-Channel Loopback Registers (PCLR1/PCLR2/PCLR3/PCLR4) represent a time slot in the outgoing frame. When these bits are set to a one, data from the corresponding receive channel will replace the data on TSER for that channel. Register Name: Register Description: Register Address: PCL1, PCL2, PCL3, PCL4 Per-Channel Loopback Enable Registers 1D0h, 1D1h, 1D2h, 1D3h [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8] (LSB) CH1 CH9 CH17 CH25 (MSB) CH8 CH16 CH24 CH32 CH7 CH15 CH23 CH31 CH6 CH14 CH22 CH30 CH5 CH13 CH21 CH29 CH4 CH12 CH20 CH28 CH3 CH11 CH19 CH27 CH2 CH10 CH18 CH26 PCL1 PCL2 PCL3 PCL4 Bits 0 to 7 / Per-Channel Loopback Enable for Channels 1 to 32 (CH1 to CH32) 0 = Loopback disabled 1 = Enable Loopback. Source data from the corresponding receive channel 228 DS26401 Octal T1/E1/J1 Framer 11.10 E1 Transmit DS0 Monitoring Function The DS26401 has the ability to monitor one DS0 64kbps channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction the user will determine which channel is to be monitored by properly setting the TCM0 to TCM4 bits in the TDS0SEL register. In the receive direction, the RCM0 to RCM4 bits in the RDS0SEL register need to be properly set. The DS0 channel pointed to by the TCM0 to TCM4 bits will appear in the Transmit DS0 Monitor (TDS0M) register and the DS0 channel pointed to by the RCM0 to RCM4 bits will appear in the Receive DS0 (RDS0M) register. The TCM4 to TCM0 and RCM4 to RCM0 bits should be programmed with the decimal decode of the appropriate T1or E1 channel. T1 channels 1 through 24 map to register values 0 through 23. E1 channels 1 through 32 map to register values 0 through 31. For example, if DS0 channel 6 in the transmit direction and DS0 channel 15 in the receive direction needed to be monitored, then the following values would be programmed into TDS0SEL and RDS0SEL: TCM4 = 0 TCM3 = 0 TCM2 = 1 TCM1 = 0 TCM0 = 1 Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 RCM4 = 0 RCM3 = 1 RCM2 = 1 RCM1 = 1 RCM0 = 0 TDS0SEL Transmit DS0 Channel Monitor Select 189h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 -- 0 4 TCM4 0 3 TCM3 0 2 TCM2 0 1 TCM1 0 0 TCM0 0 Bits 0 to 4 / Transmit Channel Monitor Bits (TCM0 to TCM4). TCM0 is the LSB of a 5 bit channel select that determines which transmit channel data will appear in the TDS0M register. Bits 5 to 7 / Unused. Must be set = 0 for proper operation. Register Name: Register Description: Register Address: Bit # Name Default 7 B1 0 TDS0M Transmit DS0 Monitor Register 1BBh + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 B2 0 5 B3 0 4 B4 0 3 B5 0 2 B6 0 1 B7 0 0 B8 0 Bits 0 to 7 / Transmit DS0 Channel Bits (B1 to B8). Transmit channel data that has been selected by the Transmit Channel Monitor Select Register. B8 is the LSB of the DS0 channel (last bit to be transmitted). 229 DS26401 Octal T1/E1/J1 Framer 11.11 E1 Transmit Signaling Operation There are two methods to provide transmit signaling data--processor-based (i.e., software-based) or hardwarebased. Processor-based refers to access through the transmit signaling registers, TS1-TS16, while hardware-based refers to using the TSIG pins. Both methods can be used simultaneously. 11.11.1 Processor-Based Mode In processor-based mode, signaling data is loaded into the Transmit Signaling registers (TS1-TS16) via the host interface. On multiframe boundaries, the contents of these registers are loaded into a shift register for placement in the appropriate bit position in the outgoing data stream. The user can utilize the Transmit Multiframe Interrupt in Latched Status Register 1 (TLS1.2) to know when to update the signaling bits. The user need not update any transmit signaling register for which there is no change of state for that register. Each Transmit Signaling Register contains the TS16 CAS signaling (E1) for one time slot that will be inserted into the outgoing stream if enabled to do so via TCR1.6. Signaling data can be sourced from the TS registers on a perchannel basis by utilizing the Software Signaling Insertion Enable registers, SSIE1 through SSIE4. In E1 mode, TS16 carries the signaling information. This information can be in either CCS (Common Channel Signaling) or CAS (Channel Associated Signaling) format. The 32 time slots are referenced by two different channel number schemes in E1. In "Channel" numbering, TS0 through TS31 are labeled channels 1 through 32. In "Phone Channel" numbering TS1 through TS15 are labeled channel 1 through channel 15 and TS17 through TS31 are labeled channel 15 through channel 30. Time Slot Numbering Schemes TS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Channel 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Phone Channel 11.11.2 Hardware-Based Mode In Hardware-Based mode, signaling data is input via the TSIG pin. This signaling PCM stream is buffered and inserted to the data stream being input at the TSER pin. Signaling data may be input via the Transmit Hardware Signaling Channel Select (THSCS) function, the framer can be set up to take the signaling data presented at the TSIG pin and insert the signaling data into the PCM data stream that is being input at the TSER pin. The user has the ability to control which channels are to have signaling data from the TSIG pin inserted into them on a per-channel basis. The signaling insertion capabilities of the framer are available whether the transmit side elastic store is enabled or disabled. If the elastic store is enabled, the backplane clock (TSYSCLK) can be 2.048MHz. If IBO mode is enabled then TSYSCLK may also be 4.096MHz, 8.192MHz, or 16.384MHz. 230 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: CAS Format (MSB) 0 0 CH1-A CH1-B CH2-A CH2-B CH3-A CH3-B CH4-A CH4-B CH5-A CH5-B CH6-A CH6-B CH7-A CH7-B CH8-A CH8-B CH9-A CH9-B CH10-A CH10-B CH11-A CH11-B CH12-A CH12-B CH13-A CH13-B CH14-A CH14-B CH15-A CH15-B CCS Format (MSB) 1 2 9 10 17 18 25 26 33 34 41 42 49 50 57 58 65 66 73 74 81 82 89 90 97 98 105 106 113 114 121 122 TS1 TO TS16 Transmit Signaling Registers (E1 MODE) 140h to 14Fh [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8] (LSB) X CH16-D CH17-D CH18-D CH19-D CH20-D CH21-D CH22-D CH23-D CH24-D CH25-D CH26-D CH27-D CH28-D CH29-D CH30-D 0 CH1-C CH2-C CH3-C CH4-C CH5-C CH6-C CH7-C CH8-C CH9-C CH10-C CH11-C CH12-C CH13-C CH14-C CH15-C 0 CH1-D CH2-D CH3-D CH4-D CH5-D CH6-D CH7-D CH8-D CH9-D CH10-D CH11-D CH12-D CH13-D CH14-D CH15-D X CH16-A CH17-A CH18-A CH19-A CH20-A CH21-A CH22-A CH23-A CH24-A CH25-A CH26-A CH27-A CH28-A CH29-A CH30-A Y CH16-B CH17-B CH18-B CH19-B CH20-B CH21-B CH22-B CH23-B CH24-B CH25-B CH26-B CH27-B CH28-B CH29-B CH30-B X CH16-C CH17-C CH18-C CH19-C CH20-C CH21-C CH22-C CH23-C CH24-C CH25-C CH26-C CH27-C CH28-C CH29-C CH30-C TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS12 TS13 TS14 TS15 TS16 3 11 19 27 35 43 51 59 67 75 83 91 99 107 115 123 4 12 20 28 36 44 52 60 68 76 84 92 100 108 116 124 5 13 21 29 37 45 53 61 69 77 85 93 101 109 117 125 6 14 22 30 38 46 54 62 70 78 86 94 102 110 118 126 7 15 23 31 39 47 55 63 71 79 87 95 103 111 119 127 (LSB) 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS12 TS13 TS14 TS15 TS16 231 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: (MSB) CH8 CH16 CH24 CH32 SSIE1, SSIE2, SSIE3, SSIE4 Software Signaling Insertion Enable Registers 118h, 119h, 11Ah, 113h [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8] (LSB) CH1 CH9 CH17 CH25 CH7 CH15 CH23 CH31 CH6 CH14 CH22 CH30 CH5 CH13 CH21 CH29 CH4 CH12 CH20 CH28 CH3 CH11 CH19 CH27 CH2 CH10 CH18 CH26 SSIE1 SSIE2 SSIE3 SSIE4 Bits 0 to 7 / Software Signaling Insertion Enable for Channels 1 to 32 (SSIEx). These bits determine which channels are to have signaling inserted form the Transmit Signaling registers. 0 = do not source signaling data from the TS registers for this channel 1 = source signaling data from the TS registers for this channel Register Name: Register Description: Register Address: (MSB) CH8 CH16 CH24 CH32 THSCS1, THSCS2, THSCS3, THSCS4 Transmit Hardware Signaling Channel Select Registers 1C8h, 1C9h, 1CAh, 1CBh [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8] (LSB) CH1 CH9 CH17 CH25 CH7 CH15 CH23 CH31 CH6 CH14 CH22 CH30 CH5 CH13 CH21 CH29 CH4 CH12 CH20 CH28 CH3 CH11 CH19 CH27 CH2 CH10 CH18 CH26 THSCS1 THSCS2 THSCS3 THSCS4 Bits 0 to 7 / Transmit Hardware Signaling Channel Select for Channels 1 to 32 (THSCSx). These bits determine which channels have signaling data inserted from the TSIG pin into the TSER PCM data. 0 = do not source signaling data from the TSIG pin for this channel 1 = source signaling data from the TSIG pin for this channel 232 DS26401 Octal T1/E1/J1 Framer 11.12 E1 Transmit Per-Channel Idle Code Insertion Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions. Thirty-two Transmit Idle Definition Registers (TIDR1-TIDR32) are provided to set the 8-bit idle code for each channel. The Transmit Channel Idle Code Enable registers (TCICE1-4) are used to enable idle code replacement on a per channel basis. Register Name: Register Description: Register Address: Bit # Name Default 7 C7 0 TIDR1 to TIDR32 Transmit Idle Code Definition Registers 1 to 32 120h to 13Fh [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8] 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Bits 0 to 7 / Per-Channel Idle Code Bits (C0 to C7). C0 is the LSB of the Code (this bit is transmitted last). Address 120H is for channel 1; address 13FH is for channel 32. Register Name: Register Description: Register Address: TCICE1, TCICE2, TCICE3, TCICE4 Transmit Channel Idle Code Enable Registers 150h, 151h, 152h, 153Hh [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8] The Transmit Channel Idle Code Enable Registers (TCICE1/2/3/4) are used to determine which of the 32 E1 channels should be overwritten with the code placed in the Transmit Idle Code Definition Register. (MSB) CH8 CH16 CH24 CH32 (LSB) CH1 CH9 CH17 CH25 CH7 CH15 CH23 CH31 CH6 CH14 CH22 CH30 CH5 CH13 CH21 CH29 CH4 CH12 CH20 CH28 CH3 CH11 CH19 CH27 CH2 CH10 CH18 CH26 TCICE1 TCICE2 TCICE3 TCICE4 Bits 0 to 7 / Transmit Channels 1 to 32 Code Insertion Control Bits (CH1 to CH32) 0 = do not insert data from the Idle Code Array into the transmit data stream 1 = insert data from the Idle Code Array into the transmit data stream 233 DS26401 Octal T1/E1/J1 Framer 11.13 E1 Transmit Channel Blocking Registers The Receive Channel blocking Registers (RCBR1 / RCBR2 / RCBR3 / RCBR4) and the Transmit Channel Blocking Registers (TCBR1 / TCBR2 / TCBR3 / TCBR4) control RCHBLK and TCHBLK pins respectively. The RCHBLK and TCHBLK pins are user-programmable outputs that can be forced either high or low during individual channels. These outputs can be used to block clocks to a USART or LAPD controller in ISDN-PRI applications. When the appropriate bits are set to a one, the RCHBLK and TCHBLK pin will be held high during the entire corresponding channel time. Register Name: Register Description: Register Address: (MSB) CH8 CH16 CH24 CH32 TCBR1, TCBR2, TCBR3, TCBR4 Transmit Channel Blocking Registers 1C4h, 1C5h, 1C6h, 1C7h [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8] (LSB) CH1 CH9 CH17 CH25 CH7 CH15 CH23 CH31 CH6 CH14 CH22 CH30 CH5 CH13 CH21 CH29 CH4 CH12 CH20 CH28 CH3 CH11 CH19 CH27 CH2 CH10 CH18 CH26 TCBR1 TCBR2 TCBR3 TCBR4 Bits 0 to 7 / Transmit Channels 1 to 32 Channel Blocking Control Bits (CH1 to CH32) 0 = force the TCHBLK pin to remain low during this channel time 1 = force the TCHBLK pin high during this channel time 234 DS26401 Octal T1/E1/J1 Framer 11.14 E1 Transmit Elastic Stores Operation The DS26401 contains dual two-frame elastic stores, one for the receive direction, and one for the transmit direction. Both elastic stores are fully independent. The transmit and receive side elastic stores can be enabled/disabled independent of each other. Also, each elastic store can interface to either a 1.544MHz or 2.048/4.096/8.192/16.384MHz backplane without regard to the backplane rate of the other elastic store. The elastic stores have two main purposes. First, they can be used for rate conversion. When the DS26401 is in the T1 mode, the elastic stores can rate convert the T1 data stream to a 2.048MHz backplane. In E1 mode, the elastic store can rate convert the E1 data stream to a 1.544MHz backplane. Secondly, they can be used to absorb the differences in frequency and phase between the T1 or E1 data stream and an asynchronous (i.e., not locked) backplane clock (which can be 1.544MHz or 2.048MHz). In this mode, the elastic stores will manage the rate difference and perform controlled slips, deleting or repeating frames of data in order to manage the difference between the network and the backplane. Note that TCBR4 will not be active when the transmitter is enabled with a 1.544MHz backplane. The elastic stores can also be used to multiplex T1 or E1 data streams into higher backplane rates. This is the Interleave Bus Option (IBO) which is discussed in Section 11.19. Note that the receive elastic store status bits are contained in TLS1 with the associated interrupt bits located in TIM1. These bits indicate a receive slip event, or when the e-store FIFO is in a `full' or `empty' condition. See the register definition for TLS1 for additional information. The operation of the transmit elastic store is very similar to the receive side. If the transmit side elastic store is enabled a 1.544MHz or 2.048MHz clock can be applied to the TSYSCLK input. The user must supply a frame sync pulse or a multiframe sync pulse to the TSSYNC input. For higher rate system clock applications, see the Interleave Bus Option section. Controlled slips in the transmit elastic store are reported in the TLS1.5 bit and the direction of the slip is reported in the TLS1.6 and TLS1.7 bits. 235 DS26401 Octal T1/E1/J1 Framer 11.14.1 Elastic Stores Initialization There are two elastic store initializations that may be used to improve performance in certain applications, Elastic Store Reset and Elastic Store Align. Both of these involve the manipulation of the elastic store's read and write pointers and are useful primarily in synchronous applications (RSYSCLK/TSYSCLK are locked to RCLK/TCLK, respectively). The elastic store reset is used to minimize the delay through the elastic store. The elastic store align bit is used to 'center' the read/write pointers to the extent possible. Elastic Store Delay After Initialization INITIALIZATION Receive Elastic Store Reset Transmit Elastic Store Reset Receive Elastic Store Align Transmit Elastic Store Align N = 9 for TSZS = 0 N = 2 for TSZS = 1 REGISTER BIT RESCR.2 TESCR.2 RESCR.3 TESCR.3 DELAY N bytes < Delay < 1 Frame + N bytes N bytes < Delay < 1 Frame + N bytes 1/2 Frame < Delay < 1 1/2 Frames 1/2 Frame < Delay < 1 1/2 Frames 11.14.2 Minimum Delay Mode Elastic store minimum delay mode may be used when the elastic store's system clock is locked to its network clock (i.e., RCLK locked to RSYSCLK for the receive side and TCLK locked to TSYSCLK for the transmit side). TESCR.1 and RESCR.1 enable the transmit and receive elastic store minimum delay modes. When enabled the elastic stores will be forced to a maximum depth of 32 bits instead of the normal two-frame depth. This feature is useful primarily in applications that interface to a 2.048MHz bus. Certain restrictions apply when minimum delay mode is used. In addition to the restriction mentioned above, RSYNC must be configured as an output when the receive elastic store is in minimum delay mode and TSYNC must be configured as an output when transmit minimum delay mode is enabled. The RSYNC and TSYNC outputs are registered on the rising edge of RSYSCLK and TSYSCLK respectfully. In a typical application RSYSCLK and TSYSCLK are locked to RCLK, and RSYNC (frame output mode) is connected to TSSYNC (frame input mode). All of the slip contention logic in the framer is disabled (since slips cannot occur). On power-up after the RSYSCLK and TSYSCLK signals have locked to their respective network clock signals, the elastic store reset bits (TESCR.2 and RESCR.2) should be toggled from a zero to a one to ensure proper operation. 236 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 TDATFMT TESCR Transmit Elastic Store Control Register 185h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 TGCLKEN 5 -- 4 TSZS 3 TESALGN 2 TESR 1 TESMDM 0 TESE 0 0 0 0 0 0 0 0 Bit 0 / Transmit Elastic Store Enable (TESE) 0 = elastic store is bypassed 1 = elastic store is enabled Bit 1 / Transmit Elastic Store Minimum Delay Mode (TESMDM) 0 = elastic stores operate at full two frame depth 1 = elastic stores operate at 32-bit depth Bit 2 / Receive Elastic Store Reset (RESR). Setting this bit from a zero to a one will force the read pointer into the same frame that the write pointer is exiting, minimizing the delay through the elastic store. If this command should place the pointers within the slip zone (see bit 4), then an immediate slip will occur and the pointers will move back to opposite frames. Should be toggled after TSYSCLK has been applied and is stable. Do not leave this bit set HIGH. Bit 3 / Transmit Elastic Store Align (TESALGN). Setting this bit from a zero to a one will force the transmit elastic store's write/read pointers to a minimum separation of half a frame. No action will be taken if the pointer separation is already greater or equal to half a frame. If pointer separation is less than half a frame, the command will be executed and the data will be disrupted. Should be toggled after TSYSCLK has been applied and is stable. Must be cleared and set again for a subsequent align. Bit 4 / Transmit Slip Zone Select (TSZS). This bit determines the minimum distance allowed between the elastic store read and write pointers before forcing a controlled slip. This bit is only applies during T1 to E1 or E1 to T1 conversion applications. 0 = force a slip at 9 bytes or less of separation (used for clustered blank channels) 1 = force a slip at 2 bytes or less of separation (used for distributed blank channels) Bit 5 / Unused. Must be set = 0 for proper operation. Bit 6 / Transmit Gapped Clock Enable (TGPCKEN). 0 = TCHCLK functions normally 1 = Enable gapped bit clock output on TCHCLK Bit 7 / Transmit Channel Data Format (TDATFMT). 0 = 64kbps (data contained in all 8 bits) 1 = 56kbps (data contained in 7 out of the 8 bits) Note: Bits 6 & 7 for fractional backplane support. 237 DS26401 Octal T1/E1/J1 Framer 11.14.3 Mapping E1 Channels from a 1.544MHz Backplane The user can use the TSCLKM bit in TIOCR.4 to enable the transmit elastic store to operate with a 1.544MHz backplane (24 channels / frame + F bit). In this mode, the user can chose which of the E1 time slots will have all ones data inserted by programming the Transmit Blank Channel Select registers (TBCS1-4). A logic 1 in the associated bit location will cause the DS26401 elastic store to force all ones at the outgoing E1 data for that channel. Typically, the user will want to program 8 channels to be 'blanked'. The default (power-up) configuration will blank channels 25 to 32, so that the first 24 E1 channels are mapped from the 24 channels of the 1.544MHz backplane. Register Name: Register Description: Register Address: (MSB) CH8 CH16 CH24 CH32 TBCS1, TBCS2, TBCS3, TBCS4 Transmit Blank Channel Select Registers 1C0h, 1C1h, 1C2h, 1C3h [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8] (LSB) CH1 CH9 CH17 CH25 CH7 CH15 CH23 CH31 CH6 CH14 CH22 CH30 CH5 CH13 CH21 CH29 CH4 CH12 CH20 CH28 CH3 CH11 CH19 CH27 CH2 CH10 CH18 CH26 TBCS1 TBCS2 TBCS3 TBCS4 Bits 0 to 7 / Transmit Blank Channel Select for Channels 1 to 32 (TBCS1 to 32) 0 = do not insert all ones for this channel 1 = insert all ones for this E1 channel 238 DS26401 Octal T1/E1/J1 Framer 11.15 Fractional E1 Support (Gapped Clock Mode) The DS26401 can be programmed to output gapped clocks for selected channels in the receive and transmit paths to simplify connections into a USART or LAPD controller in Fractional T1/E1 or ISDN-PRI applications. When the gapped clock feature is enabled, a gated clock is output on the TCHCLK signal. The channel selection is controlled via the transmit-gapped-clock channel-select registers (TGCCS1-TGCCS4). The transmit path is enabled for gapped clock mode with the TGCLKEN bit (TESCR.6). Both 56kbps and 64kbps channel formats are supported as determined by TESCR.7. When 56kbps mode is selected, the clock corresponding to the Data/Control bit in the channel is omitted (only the seven most significant bits of the channel have clocks). Register Name: Register Description: Register Address: (MSB) CH8 CH16 CH24 CH32 TGCCS1, TGCCS2, TGCCS3, TGCCS4 Transmit Gapped Clock Channel Select Registers 1CCh, 1CDh, 1CEh, 1CFh [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8] (LSB) CH1 CH9 CH17 CH25 CH7 CH15 CH23 CH31 CH6 CH14 CH22 CH30 CH5 CH13 CH21 CH29 CH4 CH12 CH20 CH28 CH3 CH11 CH19 CH27 CH2 CH10 CH18 CH26 TGCCS1 TGCCS2 TGCCS3 TGCCS4 Bits 0 to 7 / Transmit Channels 1 to 32 Gapped Clock Channel Select Bits (CH1 to CH32) 0 = no clock is present on TCHCLK during this channel time 1 = force a clock on TCHCLK during this channel time. The clock will be synchronous with TCLK if the elastic store is disabled, and synchronous with TSYSCLK if the elastic store is enabled. 239 DS26401 Octal T1/E1/J1 Framer 11.16 Additional (Sa) and International (Si) Bit Operation (E1 Mode) On the transmit side, data is sampled from the TAF and TNAF registers with the setting of the Transmit Align Frame bit in Transmit Status Register 1 (TLS1.3). The host can use the TLS1.3 bit to know when to update the TAF and TNAF registers. It has 250ms to update the data or else the old data will be retransmitted. If the TAF an TNAF registers are only being used to source the align frame and non-align frame sync patterns then the host need only write once to these registers. Data in the Si bit position will be overwritten if either the framer is programmed: (1) to source the Si bits from the TSER pin, (2) in the CRC4 mode, or (3) have automatic E-bit insertion enabled. There is also a set of eight registers (TSiAF, TSiNAF, TRA, TSa4 to TSa8) that via the Transmit Sa-Bit Control Register (TSaCR), can be programmed to insert both Si and Sa data. Data is sampled from these registers with the setting of the Transmit Multiframe bit in Status Register 1 (TLS1.3). The host can use the TLS1.3 bit to know when to update these registers. It has 2ms to update the data or else the old data will be retransmitted. 240 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 Si 0 TAF Transmit Align Frame Register 164h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 0 0 5 0 0 4 1 1 3 1 1 2 0 0 1 1 1 0 1 1 Bit 0 / Frame Alignment Signal Bit (1) Bit 1 / Frame Alignment Signal Bit (1) Bit 2 / Frame Alignment Signal Bit (0) Bit 3 / Frame Alignment Signal Bit (1) Bit 4 / Frame Alignment Signal Bit (1) Bit 5 / Frame Alignment Signal Bit (0) Bit 6 / Frame Alignment Signal Bit (0) Bit 7 International Bit (Si) Register Name: Register Description: Register Address: Bit # Name Default 7 Si 0 TNAF Transmit Non-Align Frame Register 165h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 1 1 5 A 0 4 Sa4 0 3 Sa5 0 2 Sa6 0 1 Sa7 0 0 Sa8 0 Bit 0 / Additional Bit 8 (Sa8) Bit 1 / Additional Bit 7 (Sa7) Bit 2 / Additional Bit 6 (Sa6) Bit 3 / Additional Bit 5 (Sa5) Bit 4 / Additional Bit 4 (Sa4) Bit 5 / Remote Alarm [used to transmit the alarm (A)] Bit 6 / Frame Non-Alignment Signal Bit (1) Bit 7 / International Bit (Si) 241 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 TSiF14 0 TSiAF Transmit Si Bits of the Align Frame 166h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 TSiF12 0 5 TSiF10 0 4 TSiF8 0 3 TSiF6 0 2 TSiF4 0 1 TSiF2 0 0 TSiF0 0 Bit 0 / Si Bit of Frame 0 (TSiF0) Bit 1 / Si Bit of Frame 2 (TSiF2) Bit 2 / Si Bit of Frame 4 (TSiF4) Bit 3 / Si Bit of Frame 6 (TSiF6) Bit 4 / Si Bit of Frame 8 (TSiF8) Bit 5 / Si Bit of Frame 10 (TSiF10) Bit 6 / Si Bit of Frame 12 (TSiF12) Bit 7 / Si Bit of Frame 14 (TSiF14) Register Name: Register Description: Register Address: Bit # Name Default 7 TSiF15 0 TSiNAF Transmit Si Bits of the Non-Align Frame 167h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 TSiF13 0 5 TSiF11 0 4 TSiF9 0 3 TSiF7 0 2 TSiF5 0 1 TSiF3 0 0 TSiF1 0 Bit 0 / Si Bit of Frame 1 (TSiF1) Bit 1 / Si Bit of Frame 3 (TSiF3) Bit 2 / Si Bit of Frame 5 (TSiF5) Bit 3 / Si Bit of Frame 7 (TSiF7) Bit 4 / Si Bit of Frame 9 (TSiF9) Bit 5 / Si Bit of Frame 11 (TSiF11) Bit 6 / Si Bit of Frame 13 (TSiF13) Bit 7 / Si Bit of Frame 15 (TSiF15) 242 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 TRAF15 0 TRA Transmit Remote Alarm 168h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 TRAF13 0 5 TRAF11 0 4 TRAF9 0 3 TRAF7 0 2 TRAF5 0 1 TRAF3 0 0 TRAF1 0 Bit 0 / Remote Alarm Bit of Frame 1 (TRAF1) Bit 1 / Remote Alarm Bit of Frame 3 (TRAF3) Bit 2 / Remote Alarm Bit of Frame 5 (TRAF5) Bit 3 / Remote Alarm Bit of Frame 7 (TRAF7) Bit 4 / Remote Alarm Bit of Frame 9 (TRAF9) Bit 5 / Remote Alarm Bit of Frame 11 (TRAF11) Bit 6 / Remote Alarm Bit of Frame 13 (TRAF13) Bit 7 / Remote Alarm Bit of Frame 15 (TRAF15) Register Name: Register Description: Register Address: Bit # Name Default 7 TSa4F15 TSa4 Transmit Sa4 Bits 169h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 TSa4F13 5 TSa4F11 4 TSa4F9 3 TSa4F7 2 TSa4F5 1 TSa4F3 0 TSa4F1 0 0 0 0 0 0 0 0 Bit 0 / Sa4 Bit of Frame 1 (TSa4F1) Bit 1 / Sa4 Bit of Frame 3 (TSa4F3) Bit 2 / Sa4 Bit of Frame 5 (TSa4F5) Bit 3 / Sa4 Bit of Frame 7 (TSa4F7) Bit 4 / Sa4 Bit of Frame 9 (TSa4F9) Bit 5 / Sa4 Bit of Frame 11 (TSa4F11) Bit 6 / Sa4 Bit of Frame 13 (TSa4F13) Bit 7 / Sa4 Bit of Frame 15 (TSa4F15) 243 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 TSa5F15 TSa5 Transmitted Sa5 Bits 16Ah + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 TSa5F13 5 TSa5F11 4 TSa5F9 3 TSa5F7 2 TSa5F5 1 TSa5F3 0 TSa5F1 0 0 0 0 0 0 0 0 Bit 0 / Sa5 Bit of Frame 1 (TSa5F1) Bit 1 / Sa5 Bit of Frame 3 (TSa5F3) Bit 2 / Sa5 Bit of Frame 5 (TSa5F5) Bit 3 / Sa5 Bit of Frame 7 (TSa5F7) Bit 4 / Sa5 Bit of Frame 9 (TSa5F9) Bit 5 / Sa5 Bit of Frame 11 (TSa5F11) Bit 6 / Sa5 Bit of Frame 13 (TSa5F13) Bit 7 / Sa5 Bit of Frame 15 (TSa5F15) Register Name: Register Description: Register Address: Bit # Name Default 7 TSa6F15 TSa6 Transmit Sa6 Bits 16Bh + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 TSa6F13 5 TSa6F11 4 TSa6F9 3 TSa6F7 2 TSa6F5 1 TSa6F3 0 TSa6F1 0 0 0 0 0 0 0 0 Bit 0 / Sa6 Bit of Frame 1 (TSa6F1) Bit 1 / Sa6 Bit of Frame 3 (TSa6F3) Bit 2 / Sa6 Bit of Frame 5 (TSa6F5) Bit 3 / Sa6 Bit of Frame 7 (TSa6F7) Bit 4 / Sa6 Bit of Frame 9 (TSa6F9) Bit 5 / Sa6 Bit of Frame 11 (TSa6F11) Bit 6 / Sa6 Bit of Frame 13 (TSa6F13) Bit 7 / Sa6 Bit of Frame 15 (TSa6F15) 244 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 TSa7F15 TSa7 Transmit Sa7 Bits 16Ch + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 TSa7F13 5 TSa7F11 4 TSa7F9 3 TSa7F7 2 TSa7F5 1 TSa7F3 0 TSa7F1 0 0 0 0 0 0 0 0 Bit 0 / Sa7 Bit of Frame 1 (TSa7F1) Bit 1 / Sa7 Bit of Frame 3 (TSa7F3) Bit 2 / Sa7 Bit of Frame 5 (TSa7F5) Bit 3 / Sa7 Bit of Frame 7 (TSa7F7) Bit 4 / Sa7 Bit of Frame 9 (TSa7F9) Bit 5 / Sa7 Bit of Frame 11 (TSa7F11) Bit 6 / Sa7 Bit of Frame 13 (TSa7F13) Bit 7 / Sa7 Bit of Frame 15 (TSa4F15) Register Name: Register Description: Register Address: Bit # Name Default 7 TSa8F15 TSa8 Transmit Sa8 Bits 16Dh + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 TSa8F13 5 TSa8F11 4 TSa8F9 3 TSa8F7 2 TSa8F5 1 TSa8F3 0 TSa8F1 0 0 0 0 0 0 0 0 Bit 0 / Sa8 Bit of Frame 1 (TSa8F1) Bit 1 / Sa8 Bit of Frame 3 (TSa8F3) Bit 2 / Sa8 Bit of Frame 5 (TSa8F5) Bit 3 / Sa8 Bit of Frame 7 (TSa8F7) Bit 4 / Sa8 Bit of Frame 9 (TSa8F9) Bit 5 / Sa8 Bit of Frame 11 (TSa8F11) Bit 6 / Sa8 Bit of Frame 13 (TSa8F13) Bit 7 / Sa8 Bit of Frame 15 (TSa8F15) 245 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 SiAF 0 TSACR Transmit Sa Bit Control Register 114h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 SiNAF 0 5 RA 0 4 Sa4 0 3 Sa5 0 2 Sa6 0 1 Sa7 0 0 Sa8 0 Bit 0 / Additional Bit 8 Insertion Control Bit (Sa8) 0 = do not insert data from the TSa8 register into the transmit data stream 1 = insert data from the TSa8 register into the transmit data stream Bit 1 / Additional Bit 7 Insertion Control Bit (Sa7) 0 = do not insert data from the TSa7 register into the transmit data stream 1 = insert data from the TSa7 register into the transmit data stream Bit 2 / Additional Bit 6 Insertion Control Bit (Sa6) 0 = do not insert data from the TSa6 register into the transmit data stream 1 = insert data from the TSa6 register into the transmit data stream Bit 3 / Additional Bit 5 Insertion Control Bit (Sa5) 0 = do not insert data from the TSa5 register into the transmit data stream 1 = insert data from the TSa5 register into the transmit data stream Bit 4 / Additional Bit 4 Insertion Control Bit (Sa4) 0 = do not insert data from the TSa4 register into the transmit data stream 1 = insert data from the TSa4 register into the transmit data stream Bit 5 / Remote Alarm Insertion Control Bit (RA) 0 = do not insert data from the TRA register into the transmit data stream 1 = insert data from the TRA register into the transmit data stream Bit 6 / International Bit in Non-Align Frame Insertion Control Bit (SiNAF) 0 = do not insert data from the TSiNAF register into the transmit data stream 1 = insert data from the TSiNAF register into the transmit data stream Bit 7 / International Bit in Align Frame Insertion Control Bit (SiAF) 0 = do not insert data from the TSiAF register into the transmit data stream 1 = insert data from the TSiAF register into the transmit data stream 246 DS26401 Octal T1/E1/J1 Framer 11.17 Transmit HDLC Controller Each framer port has an HDLC controller with 64-byte FIFOs. The HDLC controller can be mapped into a single time slot, or Sa4 to Sa8 bits (E1 Mode) or the FDL (T1 mode). This block has 64 byte FIFO buffers in both the transmit and receive paths. The user can select any specific bits within the time slot(s) to assign to the HDLC controller, as well as specific Sa bits (E1 mode). The HDLC controllers automatically generate and detect flags, generate and check the CRC checksum, generate and detect abort sequences, stuff and destuff zeros, and byte align to the data stream. 247 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 NOFS 0 THC1 Transmit HDLC Control Register 1 110h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 TEOML 0 5 THR 0 4 THMS 0 3 TFS 0 2 TEOM 0 1 TZSD 0 0 TCRCD 0 Bit 0 / Transmit CRC Defeat (TCRCD). A 2-byte CRC code is automatically appended to the outbound message. This bit can be used to disable the CRC function. 0 = enable CRC generation (normal operation) 1 = disable CRC generation Bit 1 / Transmit Zero Stuffer Defeat (TZSD). The Zero Stuffer function automatically inserts a zero in the message field (between the flags) after 5 consecutive ones to prevent the emulation of a flag or abort sequence by the data pattern. The receiver automatically removes (destuffs) any zero after 5 ones in the message field. 0 = enable the zero stuffer (normal operation) 1 = disable the zero stuffer Bit 2 / Transmit End of Message (TEOM). Should be set to a one just before the last data byte of an HDLC packet is written into the transmit FIFO at THF. If not disabled via TCRCD, the transmitter will automatically append a 2byte CRC code to the end of the message. Bit 3 / Transmit Flag/Idle Select (TFS). This bit selects the inter-message fill character after the closing and before the opening flags (7Eh). 0 = 7Eh 1 = FFh Bit 4 / Transmit HDLC Mapping Select (THMS) 0 = Transmit HDLC assigned to channels 1 = Transmit HDLC assigned to FDL(T1 mode), Sa Bits(E1 mode) Bit 5 / Transmit HDLC Reset (THR). Will reset the transmit HDLC controller and flush the transmit FIFO. An abort followed by 7Eh or FFh flags/idle will be transmitted until a new packet is initiated by writing new data into the FIFO. Must be cleared and set again for a subsequent reset. 0 = Normal operation 1 = Reset transmit HDLC controller and flush the transmit FIFO Bit 6 / Transmit End of Message and Loop (TEOML). To loop on a message, should be set to a one just before the last data byte of an HDLC packet is written into the transmit FIFO. The message will repeat until the user clears this bit or a new message is written to the transmit FIFO. If the host clears the bit, the looping message will complete then flags will be transmitted until new message is written to the FIFO. If the host terminates the loop by writing a new message to the FIFO the loop will terminate, one or two flags will be transmitted and the new message will start. If not disabled via TCRCD, the transmitter will automatically append a 2-byte CRC code to the end of all messages. Bit 7 / Number Of Flags Select (NOFS) 0 = send one flag between consecutive messages 1 = send two flags between consecutive messages 248 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 TABT 0 THC2 Transmit HDLC Control Register 2 113h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 THCEN 0 4 THCS4 0 3 THCS3 0 2 THCS2 0 1 THCS1 0 0 THCS0 0 Bits 0 to 4 / Transmit HDLC Channel Select (THCS0 to 4). Determines which DSO channel will have the carry the HDLC message if enabled. Bit 5 / Transmit HDLC Controller Enable (THCEN) 0 = Transmit HDLC Controller is not enabled 1 = Transmit HDLC Controller is enabled Bit 6 / Unused Bit 7 / Transmit Abort (TABT). A 0-to-1 transition will cause the FIFO contents to be dumped and one FEh abort to be sent followed by 7Eh or FFh flags/idle until a new packet is initiated by writing new data into the FIFO. Must be cleared and set again for a subsequent abort to be sent. Register Name: Register Description: Register Address: Bit # Name Default 7 TBSE8 0 THBSE Transmit HDLC Bit Suppress 111h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 TBSE7 0 5 TBSE6 0 4 TBSE5 0 3 TBSE4 0 2 TBSE3 0 1 TBSE2 0 0 TBSE1 0 Bit 0 / Transmit Bit 1 Suppress/Sa8 Bit Suppress (TBSE1). LSB of the channel. Set to one to stop this bit from being used. Bit 1 / Transmit Bit 2 Suppress/Sa7 Bit Suppress (TBSE2). Set to one to stop this bit from being used Bit 2 / Transmit Bit 3 Suppress/Sa6 Bit Suppress (TBSE3). Set to one to stop this bit from being used Bit 3 / Transmit Bit 4 Suppress/Sa5 Bit Suppress (TBSE4). Set to one to stop this bit from being used Bit 4 / Transmit Bit 5 Suppress/Sa4 Bit Suppress (TBSE5). Set to one to stop this bit from being used Bit 5 / Transmit Bit 6 Suppress (TBSE6). Set to one to stop this bit from being used. Bit 6 / Transmit Bit 7 Suppress (TBSE7). Set to one to stop this bit from being used. Bit 7 / Transmit Bit 8 Suppress (TBSE8). MSB of the channel. Set to one to stop this bit from being used. 249 DS26401 Octal T1/E1/J1 Framer 11.17.1 Transmit HDLC FIFO Control Control of the transmit FIFO is accomplished via the Transmit HDLC FIFO Control (THFC). The FIFO Control register sets the watermarks for the receive FIFO. When the transmit FIFO empties below the low watermark, the TLWM bit in the appropriate HDLC status register will be set. TLWM is a real-time bit and will remain set as long as the transmit FIFO's write pointer is below the watermark. If enabled, this condition can also cause an interrupt via the INT pin. Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 THFC Transmit HDLC FIFO Control Register 187h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 -- 0 1 TFLWM1 0 0 TFLWM0 0 Bits 0, 1 / Transmit HDLC FIFO Low-Watermark Select (TFLWM0 to TFLWM1) TFLWM1 0 0 1 1 TFLWM0 0 1 0 1 Transmit FIFO Watermark 4 bytes 16 bytes 32 bytes 48 bytes Bits 2-7 / Unused. Must be set = 0 for proper operation. 250 DS26401 Octal T1/E1/J1 Framer 11.17.2 HDLC Status and Information TLS2 provides status information for the transmit HDLC controller. When a particular event has occurred (or is occurring), the appropriate bit in one of these registers will be set to a one. Some of the bits in these registers are latched and some are real-time bits that are not latched. This section contains register descriptions that list which bits are latched and which are real time. With the latched bits, when an event occurs and a bit is set to a one, it will remain set until the user reads that bit. The bit will be cleared when it is read and it will not be set again until the event has occurred again. The real-time bits report the current instantaneous conditions that are occurring and the history of these bits is not latched. Like the other latched status registers, the user will follow a read of the status bit with a write. The byte written to the register will inform the device which of the latched bits the user wishes to clear (the real time bits are not affected by writing to the status register). The user will write a byte to one of these registers, with a one in the bit positions he or she wishes to clear and a zero in the bit positions he or she does not wish to clear. The HDLC status register, TLS2 has the ability to initiate a hardware interrupt via the INT output signal. Each of the events in this register can be either masked or unmasked from the interrupt pin via the receive HDLC Interrupt Mask Register (TIM2). Interrupts will force the INT signal low when the event occurs. The INT pin will be allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the interrupt to occur. Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 TRTS2 Transmit Real-Time Status Register 2 (HDLC) 1B1h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 -- 0 4 -- 0 3 TEMPTY 0 2 TFULL 0 1 TLWM 0 0 TNF 0 All bits in this register are real time. Bit 0 / Transmit FIFO Not Full Condition (TNF). Set when the transmit 64-byte FIFO has at least one byte available. Bit 1 / Transmit FIFO Below Low-Watermark Condition (TLWM). Set when the transmit 64-byte FIFO empties below the low watermark as defined by the Transmit Low-Watermark bits (TLWM). Bit 2 / Transmit FIFO Full (TFULL). A real-time bit that is set high when the FIFO is full. Bit 3 / Transmit FIFO Empty (TEMPTY). A real-time bit that is set high when the FIFO is empty. Bits 4-7 / Unused 251 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 TLS2 Transmit Latched Status Register 2 (HDLC) 191h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 -- 0 4 -- 0 3 TUDR 0 2 TMEND 0 1 TLWMS 0 0 TNFS 0 All bits in this register are latched and can create interrupts. Bit 0 / Transmit FIFO Not Full Set Condition (TNFS). Set when the transmit 64-byte FIFO has at least one empty byte available for write. Rising edge detect of TNF. Indicates change of state from full to not full. Bit 1 / Transmit FIFO Below Low-Watermark Set Condition (TLWMS). Set when the transmit 64-byte FIFO empties beyond the low watermark as defined by the Transmit Low-Watermark bits (TLWM) (rising edge detect of TLWM). Bit 2 / Transmit Message End Event (TMEND). Set when the transmit HDLC controller has finished sending a message. Bit 3 / Transmit FIFO Underrun Event (TUDR). Set when the transmit FIFO empties out without having seen the TMEND bit set. An abort is automatically sent. Bits 4 to 7 / Unused 252 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 TIM2 Transmit Interrupt Mask Register 2 1A1h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 -- 0 4 -- 0 3 TUDR 0 2 TMEND 0 1 TLWMS 0 0 TNFS 0 Bit 0 / Transmit FIFO Not Full Set Condition (TNFS) 0 = interrupt masked 1 = interrupt enabled Bit 1 / Transmit FIFO Below Low Watermark Set Condition (TLWMS) 0 = interrupt masked 1 = interrupt enabled Bit 2 / Transmit Message End Event (TMEND) 0 = interrupt masked 1 = interrupt enabled Bit 3 / Transmit FIFO Underrun Event (TUDR) 0 = interrupt masked 1 = interrupt enabled Bits 4 to 7 / Unused. Must be set = 0 for proper operation. 253 DS26401 Octal T1/E1/J1 Framer 11.17.3 FIFO Information The Transmit FIFO Buffer Available register indicates the number of bytes that can be written into the transmit FIFO. The count form this register informs the host as to how many bytes can be written into the transmit FIFO without overflowing the buffer. This is a real-time register. The count shall remain valid and stable during the read cycle. Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 TFBA Transmit HDLC FIFO Buffer Available 1B3h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 TFBA6 0 5 TFBA5 0 4 TFBA4 0 3 TFBA3 0 2 TFBA2 0 1 TFBA1 0 0 TFBA0 0 Bits 0-6 / Transmit FIFO Bytes Available (TFBAO to TFBA6). TFBA0 is the LSB. Register Name: Register Description: Register Address: Bit # Name Default 7 THD7 0 THF Transmit HDLC FIFO 1B4h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 THD6 0 5 THD5 0 4 THD4 0 3 THD3 0 2 THD2 0 1 THD1 0 0 THD0 0 Bit 0 / Transmit HDLC Data Bit 0 (THD0). LSB of a HDLC packet data byte. Bit 1 / Transmit HDLC Data Bit 1 (THD1) Bit 2 / Transmit HDLC Data Bit 2 (THD2) Bit 3 / Transmit HDLC Data Bit 3 (THD3) Bit 4 / Transmit HDLC Data Bit 4 (THD4) Bit 5 / Transmit HDLC Data Bit 5 (THD5) Bit 6 / Transmit HDLC Data Bit 6 (THD6) Bit 7 / Transmit HDLC Data Bit 7 (THD7). MSB of a HDLC packet data byte. 254 DS26401 Octal T1/E1/J1 Framer 11.18 HDLC Transmit Example The HDLC status registers in the DS26401 allow for flexible software interface to meet the user's preferences. When transmitting HDLC messages, the host can choose to be interrupt driven, or to poll to desired status registers, or a combination of polling and interrupt processes may be used. An example routine for using the DS26401 HDLC receiver is given in Figure 11-1. Figure 11-1. HDLC Message Transmit Example Configure Transmit HDLC Controller (THC1,THC2,THBSE,THFC) Reset Transmit HDLC Controller (THC.5) Enable TLWM Interrupt and Verify TLWM Clear Set TEOM (THC1.2) Read TFBA N = TFBA[6..0] Push Last Byte into Tx FIFO Push Message Byte into Tx HDLC FIFO (THF) Loop N Last Byte of Message? NO TLWM Interrupt? YES NO NO YES Enable TMEND Interrupt TMEND Interrupt? YES Read TUDR Status Bit NO A A TUDR = 1 A YES No Action Required Work Another Process Disable TMEND Interrupt Prepare New Message Disable TMEND Interrupt Resend Message 255 DS26401 Octal T1/E1/J1 Framer 11.19 Interleaved PCM Bus Operation (IBO) In many architectures, the PCM outputs of individual framers are combined into higher speed PCM buses to simplify transport across the system backplane. The DS26401 can be configured to allow PCM data to be multiplexed into higher speed buses eliminating external hardware, saving board space and cost. The DS26401 can be configured for channel or frame interleave. The interleaved PCM bus option (IBO) supports three bus speeds. The 4.096 MHz bus speed allows two PCM data streams to share a common bus. The 8.192 MHz bus speed allows four PCM data streams to share a common bus. The 16.384 MHz bus speed allows 8 PCM data streams to share a common bus. The receive elastic stores of each transceiver must be enabled. Via the IBO register the user can configure each framer for a specific bus position. For all IBO bus configurations each framer is assigned an exclusive position in the high speed PCM bus. The 8kHz frame sync can be generated from the system backplane or from the first device on the bus. All other devices on the bus must have their frame syncs configured as inputs. Relative to this common frame sync, the devices will await their turn to drive or sample the bus according to the settings of the DA0, DA1 and DA2 bits of the TIBOC register. 11.19.1 Channel Interleave In channel interleave mode data is output to the PCM Data Out bus one channel at a time from each of the connected DS26401s until all channels of frame n from each framer has been placed on the bus. This mode can be used even when the DS26401s are operating asynchronous to each other. The elastic stores will manage slip conditions. The DS26401 provides an active low signal (TIBO_OEB) during bus active times. TIBO_OEB can be used for bus multiplexer or tri-state buffer control. 11.19.2 Frame Interleave In frame interleave mode data is output to the PCM Data Out bus one frame at a time from each of the framers. This mode is used only when all connected DS26401s are operating in a synchronous fashion (all inbound T1 or E1 lines are synchronous) and are synchronous with the system clock (system clock derived from T1 or E1 line). In this mode, slip conditions are not allowed. 256 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 TIBOC Transmit Interleave Bus Operation Control Register 188h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 IBS1 0 5 IBS0 0 4 IBOSEL 0 3 IBOEN 0 2 DA2 0 1 DA1 0 0 DA0 0 Bits 0 to 2 / Device Assignment Bits (DA0 to DA2) DA2 0 0 0 0 1 1 1 1 DA1 0 0 1 1 0 0 1 1 DA0 0 1 0 1 0 1 0 1 Device Position 1st Device on bus 2nd Device on bus 3rd Device on bus 4th Device on bus 5th Device on bus 6th Device on bus 7th Device on bus 8th Device on bus Bit 3 / Interleave Bus Operation Enable (IBOEN) 0 = Interleave Bus Operation disabled. 1 = Interleave Bus Operation enabled. Bit 4 / Interleave Bus Operation Select (IBOSEL). This bit selects channel or frame interleave mode. 0 = Channel Interleave 1 = Frame Interleave Bits 5 to 6 / IBO Bus Size Bit 1 (IBS0 to IBS1). Indicates how many devices on the bus. IBS1 0 0 1 1 IBS0 0 1 0 1 Bus Size 2 Devices on bus 4 Devices on bus 8 Devices on bus Reserved for future use Bit 7 / Unused. Must be set = 0 for proper operation. 257 DS26401 Octal T1/E1/J1 Framer 11.20 Interfacing the E1 Transmitter to the BERT Data from the on-chip BERT can be ported to the transmit formatter by using the registers described below. Any single DS0 or combination of DS0s can be inserted into the data stream up to the entire T1 payload as controlled by the RBCS registers. Note that one BERT resource is shared among all 8 framers. Therefore the TBEN bit should be set for only one framer at a time. If multiple framers have the TBEN bit set, the lower number framer is assigned the resource. Details concerning the on-chip BERT can be found in Section 12. Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 TBICR Transmit BERT Interface Control Register 18Ah + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 TBDC 0 1 -- 0 0 TBEN 0 Bit 0 / Transmit BERT Enable (TBEN) 0 = Transmit BERT is not assigned to this framer 1 = Transmit BERT is assigned to this framer Bits 1, 3 to 7 / Unused. Must be set = 0 for proper operation. Bit 2 / Transmit BERT Direction Control (TBDC) 0 = Transmit Path: The BERT transmits toward the network via the TPOS and TNEG pins. 1 = Backplane: The BERT transmits toward the system backplane via the RSER pin. 258 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: TBCS1, TBCS2, TBCS3, TBCS4 Transmit BERT Channel Select Registers 1D4h, 1D5h, 1D6h, 1D7h [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8] Setting any of the CH1 through CH32 bits in the TBCS1 through TBCS4 registers will map data into those channels from the on-board BERT. TBEN must be set to one for these registers to have effect. Multiple, or all channels may be selected simultaneously. These registers work with the transmit-side framer only. (MSB) CH8 CH16 CH24 CH32 (LSB) CH1 CH9 CH17 CH25 CH7 CH15 CH23 CH31 CH6 CH14 CH22 CH30 CH5 CH13 CH21 CH29 CH4 CH12 CH20 CH28 CH3 CH11 CH19 CH27 CH2 CH10 CH18 CH26 TBCS1 TBCS2 TBCS3 TBCS4 Register Name: Register Description: Register Address: Bit # Name Default 7 BSE8 0 TBBS Transmit BERT Bit Suppress Register 18Bh 6 BSE7 0 5 BSE6 0 4 BSE5 0 3 BSE4 0 2 BSE3 0 1 BSE2 0 0 BSE1 0 Bit 0 / Transmit Channel Bit 1 Suppress (BSE1). LSB of the channel. Set to one to stop this bit from being used. Bit 1 / Transmit Channel Bit 2 Suppress (BSE2). Set to one to stop this bit from being used. Bit 2 / Transmit Channel Bit 3 Suppress (BSE3). Set to one to stop this bit from being used. Bit 3 / Transmit Channel Bit 4 Suppress (BSE4). Set to one to stop this bit from being used. Bit 4 / Transmit Channel Bit 5 Suppress (BSE5). Set to one to stop this bit from being used. Bit 5 / Transmit Channel Bit 6 Suppress (BSE6). Set to one to stop this bit from being used. Bit 6 / Transmit Channel Bit 7 Suppress (BSE7). Set to one to stop this bit from being used. Bit 7 / Transmit Channel Bit 8 Suppress (BSE8). MSB of the channel. Set to one to stop this bit from being used. 259 DS26401 Octal T1/E1/J1 Framer 11.21 E1 Transmit Synchronizer The DS26401 transmitter has the ability to identify the E1 frame boundary, as well as the CRC multiframe boundaries within the incoming NRZ data stream at TSER. Control signals for the transmit synchronizer are located in the TSYNCC register. The Transmit Synchronizer Status (TSYNCS) register provides a latched status bit (LOFD) to indicate that a loss-of-frame synchronization has occurred, and a real-time bit (LOF) which is set high when the synchronizer is searching for frame/multiframe alignment. The LOFD bit can be enabled to cause an interrupt condition on INT. Note that when the transmit synchronizer is used, the TSYNC signal should be set as an output (TSIO = 1) and the recovered frame sync pulse will be output on this signal. The recovered CRC4 multiframe sync pulse will be output if enabled with TIOCR.0 (TSM = 1). The transmit synchronizer cannot be used while the transmit elastic store is enabled. Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 TSYNCC Transmit Synchronizer Control Register 18Eh + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 -- 0 4 -- 0 3 CRC4 0 2 TSEN 0 1 SYNCE 0 0 RESYNC 0 Bit 0 / Resynchronize (RESYNC). When toggled from low to high, a resynchronization of the transmit-side framer is initiated. Must be cleared and set again for a subsequent resync. Bit 1 / Sync Enable (SYNCE) 0 = auto resync enabled 1 = auto resync disabled Bit 2 / Transmit Synchronizer Enable (TSEN) 0 = transmit synchronizer disabled 1 = transmit synchronizer enabled Bit 3 / CRC4 Enable (RCRC4) 0 = CRC4 disabled 1 = CRC4 enabled Bits 4 to 7 / Unused. Must be set = 0 for proper operation. 260 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 TLS3 Transmit Latched Status Register 3 (Synchronizer) 192h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 -- 0 1 LOF 0 0 LOFD 0 Bit 0 / Loss-of-Frame Synchronization Detect (LOFD). This latched bit is set when the transmit synchronizer is searching for the sync pattern in the incoming data stream. Bit 1 / Loss of Frame (LOF). A real-time bit that indicates that the transmit synchronizer is searching for the sync pattern in the incoming data stream. Bits 2 to 7 / Unused Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 TIM3 Transmit Interrupt Mask Register 3 (Synchronizer) 1A2h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 -- 0 1 -- 0 0 LOFD 0 Bit 0 / Loss-of-Frame Synchronization Detect (LOFD) 0 = Interrupt masked 1 = Interrupt enabled Bits 1 to 7 / Unused. Must be set = 0 for proper operation. 261 DS26401 Octal T1/E1/J1 Framer 12. BERT 12.1 BERT Registers ADDRESS 2F0 2F1 2F2 2F3 2F4 2F5 2F6 2F7 2F8 2F9 2FA 2FB 2FC 2FD 2FE 2FF NAME BCR1 BCR2 BCR3 BCR4 BSR BTSR1 BTSR2 BTSR3 BTSR4 BTR BCNT1 BCNT2 BCNT3 BCNT4 BCNT5 BCNT6 TYPE R/W R/W R/W R/W R R/W R/W R/W R/W R/W R R R R R R FUNCTION BERT Control Register 1 BERT Control Register 2 BERT Control Register 3 BERT Control Register 4 BERT Status Register BERT Tap/Seed Register 1 BERT Tap/Seed Register 2 BERT Tap/Seed Register 3 BERT Tap/Seed Register 4 BERT TEST Register BERT Count Register 1 BERT Count Register 2 BERT Count Register 3 BERT Count Register 4 BERT Count Register 5 BERT Count Register 6 PAGE 267 268 269 270 271 272 272 272 272 264 274 274 274 274 274 274 262 DS26401 Octal T1/E1/J1 Framer 12.2 BERT Description and Operation The DS26401 contains a full-feature BERT (bit error-rate tester) that can be enabled for use with any T1/E1 port of the device. The on-chip BERT can generate and detect both pseudorandom and repeating bit patterns. The BERT block can generate and detect the following patterns: * * * Maximal-length pseudorandom patterns up to 2 - 1 Repetitive patterns in any length up to 512 octets QRSS pattern per T1.403 32 The BERT function is assigned on a per-channel basis for both the transmitter and receiver. This is accomplished by using the BERT expansion port control and channel select registers within the DS26401. Using this function, the BERT pattern can be transmitted and/or received in single or across multiple DS0s, contiguous or broken. Transmit and receive bandwidth assignments are independent of each other. The BERT resource is shared between the eight framers of the DS26401, and the BERT transmitter and receiver can be independently assigned to different ports of the octal framer if desired. BSR contains the status information on the BERT function. The host can be alerted when there is a change of state of the BERT via this register. A major change of state is defined as either a change in the receive synchronization (i.e., the BERT has gone into or out of receive synchronization), a bit error has been detected, or an overflow has occurred in either the Bit Counter or the Error Counter. The host must read the BERT Status Register (BSR) to determine the change of state. 263 DS26401 Octal T1/E1/J1 Framer 12.3 Pattern Generation 12.3.1 Polynomial Generation The internal BERT has a 32-bit TAP register (BTR) used to tap up to 32 bits in the feedback path of the polynomial generator. The BERT also contains a 32-bit Seed register used to preset the polynomial generator with an initial value. The Seed values are latched on the rising edge of the TL control bit in BCR1. The internal BERT can generate polynomial patterns of any length up to and including 2 - 1. All the industry standard polynomials can be programmed using the control registers (some examples are given in Table 16-1). The polynomial is generated using a shift register of programmable length and programmable feed back tap positions. The user has access to all combination of pattern length and pattern tap locations to generate industry standard polynomials or other combinations as well. In addition, the QRSS pattern described in T1.403 is supported 20 by setting the QRSS bit in BCR1. The T1.403 QRSS pattern is the polynomial 2 - 1 with the additional requirement that "an output bit is forced to ONE whenever the next 14 bits are ZERO." 32 12.3.2 Repetitive Pattern Generation In addition to polynomial patterns, the BERT can generate repetitive patterns of considerable length. The host has access to 512 bytes of memory for storing pattern. The End Repetitive Address registers (04h, and 05h) are used to program the length of the pattern itself. Memory is addressed indirectly and is used to store the pattern. Data can be sent MSB or LSB first as it appears in the memory. Repetitive patterns can include simple patterns such as 3 in 24, but the additional memory can be used to store patterns such as DDS-n patterns or T1-n patterns. Repetitive patterns are stored in increments of 8 bits. In order to generate a repetitive pattern that is 12 bits long (3 nibbles), the pattern is written twice such that the pattern is 24 bits long (3 bytes), and repeats twice in memory. The same is true when the device is used in serial mode, a 5-bit pattern is written to memory 5 times. For example: To generate a 00001 pattern at the serial output: Write these bytes to memory: RAM ADDRESS 00h 01h 02h 03h 04h BINARY CODE 00010000 01000010 00001000 00100001 10000100 HEX CODE 10h 42h 08h 21h 84h 264 DS26401 Octal T1/E1/J1 Framer 12.4 Pattern Synchronization 12.4.1 Synchronization The receiver synchronizes to the same pattern that is being transmitted. The pattern must be error-free when the synchronizer is on line. 12.4.1.1 Polynomial Synchronization Synchronization to polynomial patterns takes 50 + n clock cycles, where n is the exponent in the polynomial that describes the pattern. Once synchronized, any bit that does not match the polynomial is counted as a bit error. 12.4.1.2 Repetitive Pattern Synchronization Synchronization to repetitive patterns can take several complete repetitions of the entire pattern. The actual sync time depends on the nature of the pattern and the location of the synchronization pointer. Errors that occur during synchronization could affect the sync time; at least one complete error-free repetition must be received before synchronization is declared. Once synchronized, any bit that does not match the pattern that is programmed in the on-board RAM is counted as a bit error. 12.5 BER Calculation 12.5.1 Counters The bit counter is active at all times. Once synchronized, the error counters come on line. The receiver has large 48-bit count registers. These counters accumulate for 50,640 hours at the T1 line rate, 1.544MHz, and 38,170 hours at the E1 line rate, 2.048MHz. To accumulate BER data, the user toggles the LC bit at T = 0. This clears the accumulators and loads the contents into the count registers. At T = 0, these results should be ignored. At this point, the device is counting bits and bit errors. At the end of the specified time interval, the user toggles the LC bit again and reads the count registers. These are the valid results used to calculate a bit-error rate. 12.6 Error Generation The BERT can insert bit errors at a particular rate by setting the error insertion bits in Control Register 2. Injecting errors allows users to stress communication links and to check the functionality of error monitoring equipment along the path. In addition, the device can insert errors on command by setting the SBE bit in Control Register 2. The bit that occurs after the rising edge of the SBE insert bit is inverted. In the case of the QRSS pattern, this could result in a string of zeros longer than 14 bits; the DS26104 delays the erred bit by one clock cycle. 265 DS26401 Octal T1/E1/J1 Framer Figure 12-1. Shared BERT Block Diagram CR1.5 LC Bit Counter Error Counter RCLK_EN Loopback MUX SYNC CR1.0 TL Pattern Detector Receive Rate Control RCLK RDAT[7:0] 2n-1 Error Insertion Repetitive Pattern Generator Transmit Rate Control TCLK_EN TCLK TDAT[7:0] TCLK0 Parallel Control Port CS RD WR A[3:0] D[7:0] 266 DS26401 Octal T1/E1/J1 Framer 12.7 BERT Control Registers Register Name: Register Description: Register Address: Bit # Name Default 7 BSYNCE 0 BCR1 BERT Control Register 1 2F0h 6 BRESYNC 0 5 LC 0 4 LPBK 0 3 QRSS 0 2 PS 0 1 LSB 0 0 TL 0 Bit 0 / Transmit Load (TL). A rising edge causes the transmit shift register to be loaded with the seed value. Bit 1 / LSB/MSB (LSB) 0 = Repetitive Pattern data is transmitted/received MSB first. 1 = Repetitive Pattern data is transmitted/received LSB first. Bit 2 / Pattern Select (PS) 0 = Pseudorandom pattern. 1 = Repetitive pattern. Bit 3 / Zero Suppression Select (QRSS). Forces a 1 into the pattern whenever the next 14 bit positions are all 0s. Should only be set when using the QRSS pattern. 0 = Disable 14 zero suppression. 1 = Enable 14 zero suppression per T1.403. Bit 4 / Transmit/Receive Loopback Select (LPBK) 0 = Loop back disabled. 1 = Loop back enabled. Bit 5 / Latch Count Registers (LC). A rising edge copies the bit count and bit error count accumulators to the appropriate registers. The accumulators are then cleared. Bit 6 / Initiate Manual Resync Process (BRESYNC). A rising edge causes the device to go out of sync and begin resynchronization process. Bit 7 / BERT SYNC Enable (BSYNCE) 0 = Auto resync enabled. 1 = Auto resync disabled. 267 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 BCR2 BERT Control Register 2 2F1h 6 -- 0 5 TINV 0 4 RINV 0 3 SBE 0 2 EIR2 0 1 EIR1 0 0 EIR0 0 Bits 0 to 2 / Error Insert Bits 0 to 2 (EIB0 to EIB2). Will automatically insert bit errors at the prescribed rate into the generated data pattern. Can be used for verifying error detection features. EIB2 0 0 0 0 1 1 1 1 EIB1 0 0 1 1 0 0 1 1 EIB0 0 1 0 1 0 1 0 1 Error Rate Inserted No errors automatically inserted 10E-1 10E-2 10E-3 10E-4 10E-5 10E-6 10E-7 Bit 3 / Single Bit Error Insert (SBE). A low-to-high transition creates a single bit error. Must be cleared and set again for a subsequent bit error to be inserted. Bit 4 / Receive Invert Data Enable (RINV) 0 = do not invert the incoming data stream 1 = invert the incoming data stream Bit 5 / Transmit Invert Data Enable (TINV) 0 = do not invert the outgoing data stream 1 = invert the outgoing data stream Bits 6, 7 / Unused. Must be set = 0 for proper operation. 268 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 PL7 0 BCR3 BERT Control Register 3 2F2h 6 PL6 0 5 PL5 0 4 PL4 0 3 PL3 0 2 PL2 0 1 PL1 0 0 PL0 0 Bit 0 / Pattern Length Bit 0 (PL0). Bit 0 of [8:0] end address of repetitive pattern data. Bit 1 / Pattern Length Bit 1 (PL1). Bit 1 of [8:0] end address of repetitive pattern data. Bit 2 / Pattern Length Bit 2 (PL2). Bit 2 of [8:0] end address of repetitive pattern data. Bit 3 / Pattern Length Bit 3 (PL3). Bit 3 of [8:0] end address of repetitive pattern data. Bit 4 / Pattern Length Bit 4 (PL4). Bit 4 of [8:0] end address of repetitive pattern data. Bit 5 / Pattern Length Bit 5 (PL5). Bit 5 of [8:0] end address of repetitive pattern data. Bit 6 / Pattern Length Bit 6 (PL6). Bit 6 of [8:0] end address of repetitive pattern data. Bit 7 / Pattern Length Bit 7 (PL7). Bit 7 of [8:0] end address of repetitive pattern data. 269 DS26401 Octal T1/E1/J1 Framer Register Name: Register Description: Register Address: Bit # Name Default 7 TEST 0 BCR4 BERT Control Register 4 2F3h 6 TEST 0 5 CLKINV 0 4 R/W 0 3 RAM 0 2 COUNT 0 1 SEED 0 0 PL8 0 Bit 0 / Pattern Length Bit 8 (PL8). Bit 8 (MSB) of [8:0] end address of repetitive pattern data. Bit 1 / Select Bit for Tap/Seed Registers (SEED) 0 = Registers 0F5h - 0F8h refer to Tap Select registers. 1 = Registers 0F5h - 0F8h refer to Pre-load Seed registers. Bit 2 / Select Bit for Registers Counter Registers (COUNT) 0 = Registers 0FAh - 0FFh refer to Bit Count Registers. 1 = Registers 0FAh - 0FFh refer to Error Count Registers. Bit 3 / RAM Select (RAM). This bit should be set when repetitive pattern data is being loaded into the RAM. 0 = BERT state machine has control of the RAM. 1 = Parallel port has read and write access to the RAM. Bit 4 / Read/Write Select (R/W). This bit is used with the RAM bit to read or write the RAM. 0 = Write to the RAM. 1 = Read from the RAM. Bit 5 / TCLKO Invert (CLKINV) 0 = TCLKO polarity is normal. 1 = TCLKO polarity is inverted. Bits 6, 7 / Factory use; must be set to zero. 270 DS26401 Octal T1/E1/J1 Framer 12.8 BERT Status Register The Status register contains information on the current real-time status of the BERT. When a particular event has occurred, the appropriate bit in the register is set to 1. All the bits in this register (except for BSYNC) operate in a latched fashion. This means that if an event occurs and a bit is set to a 1, it remains set until the user reads the register. For the BED, BCOF, and BECOF bits, they are cleared when read and are not set again until the event has occurred again. For RLOS, RA0, and RA1 bits, they are cleared when read if the condition no longer persists. Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 BSR BERT Status Register 2F4h 6 BRA1 0 5 BRA0 0 4 BED 0 3 BECOF 0 2 BCOF 0 1 BRLOS 0 0 BSYNC 0 Bit 0 / BERT in Synchronization Condition (BSYNC). A real-time bit that reports the BERT's synchronization status. Bit 1 / BERT Receive Loss of Sync (BRLOS). Set when the receiver is searching for synchronization. Once sync is achieved, this bit remains set until read. This bit is latched. Bit 2 / Bit Counter Overflow (BCOF). Set when the bit counter overflows. Cleared when read. Bit 3 / Bit Error Count Overflow (BECOF). Set when the bit error counter overflows. Cleared when read. Bit 4 / Bit Error Detection (BED). Set when bit error count is non-zero. Cleared when read. Bit 5 / BERT Receive All Zeros (BRA0). Set when 40 consecutive zeros are received in pseudorandom mode. Allowed to be cleared when a one is received. Bit 6 / BERT Receive All Ones (BRA1). Set when 40 consecutive ones are received in pseudorandom mode. Allowed to be cleared when a zero is received. Bit 7 / Unused. Must be set = 0 for proper operation. 271 DS26401 Octal T1/E1/J1 Framer 12.9 Pseudorandom Pattern Registers Bit 1 of Control Register 4 determines if the addresses point to the Tap Select or Seed registers. The Tap Select register is used to select the length and tap positions for pseudorandom generation/reception. Each bit that is set to 1 denotes a tap at that location for the feedback path. The highest bit location set to 1 is the length of the shift register. For example, to transmit/receive 2 - 1 (O.151) BIT14 and BIT13 would be set to 1. All other bits would be 0. Table 12-1 gives Tap Select and Seed Values for many pseudorandom patterns. The Seed Value is loaded into the transmit shift register on the rising edge of TL (CR1.0). Register Name: Register Description: Register Address: (MSB) BIT7 BIT15 BIT23 BIT31 BTSR1, BTSR2, BTSR3, BTSR4 BERT Tap/Seed Registers 2F5h, 2F6h, 2F7h, 2F8h (LSB) BIT0 BIT8 BIT16 BIT24 15 BIT6 BIT14 BIT22 BIT30 BIT5 BIT13 BIT21 BIT29 BIT4 BIT12 BIT20 BIT28 BIT3 BIT11 BIT19 BIT27 BIT2 BIT10 BIT18 BIT26 BIT1 BIT9 BIT17 BIT25 BTSR1 BTSR2 BTSR3 BTSR4 Bits 0 to 7 / BERT Tap / Seed Register Bits 0 to 31 0 = do not select a tap at this bit location / seed value = 0 for this bit position 1 = do select a tap at this bit location / seed value = 1 for this bit position 272 DS26401 Octal T1/E1/J1 Framer Table 12-1. Pseudo-Random Pattern Generation PATTERN TYPE 2 -1 2 -1 2 -1 2 -1 2 -1 Fractional T1 LB Activate 2 -1 Fractional T1 LB Deactivate 2 -1 2 -1 Maximal Length 2 -1 O.153 (511 Type) 2 -1 2 -1 O.152 and O.153 (2047 Type) 2 -1 Maximal Length 2 -1 Maximal Length 2 -1 Maximal Length 2 -1 O.151 2 -1 Maximal Length 2 -1 2 -1 2 -1 Maximal Length 2 -1 O.153 2 -1 T1.403 QRSS (CR1.3 = 1) 2 -1 2 -1 2 -1 O.151 2 -1 Maximal Length 2 -1 2 -1 Maximal Length 2 -1 Maximal Length 2 -1 2 -1 2 -1 Maximal Length 2 -1 2 -1 Maximal Length 32 31 30 29 28 27 26 25 24 23 22 21 20 20 19 18 17 16 15 14 13 12 11 10 9 8 7 7 7 6 5 4 3 TAP1 05 09 12 30 48 48 41 B8 10 40 00 29 0D 15 00 08 04 40 23 04 00 02 01 00 00 04 23 13 04 02 29 04 03 TAP2 00 00 00 00 00 00 00 00 01 02 05 08 10 20 60 D0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 TAP3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 02 04 08 09 10 20 42 E1 00 00 00 00 00 00 00 20 TAP4 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 02 04 08 10 20 40 80 SEED1/2/3/4 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF TINV 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 RINV 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 273 DS26401 Octal T1/E1/J1 Framer 12.10 Count Registers *Bit 2 of Control Register 4 determines if the addresses point to the Bit Count or Error Count registers. The Bit Count registers comprise a 48-bit count of bits (actually RCLK cycles) received. C47 is the MSB of the 48bit count. The bit counter increments for each cycle of RCLK when RCLK_EN is high. The bit counter is enabled regardless of synchronization. The Status Register bit BCOF is set when this 48-bit register overflows. The counter rolls over upon an overflow condition. The DS2174 latches the bit count into the Bit Count registers and clears the internal bit count when the LC bit in Control Register 1 is toggled from low to high. The Error Count registers maintain a 48-bit count of bits received in error. The bit error counter is disabled during loss of SYNC. C47 is the MSB of the 48-bit count. The Status register bit BECOF is set when this 48-bit register overflows. The counter rolls over upon an overflow condition. The DS2174 latches the bit count into the Bit-Error Count registers and clears the internal bit-error count when the LC bit in Control Register 1 is toggled from low to high. An external processor uses the bit count and bit-error count to compute the BER performance on a loop or channel basis. Register Name: Register Description: Register Address: (MSB) C7 C15 C23 C31 C39 C47 BCNT1, BCNT2, BCNT3, BCNT4, BCNT5, BCNT6 BERT Count Registers 2FAh, 2FBh, 2FCh, 2FDh, 2FEh, 2FFh (LSB) C0 C8 C16 C24 C32 C40 C6 C14 C22 C30 C38 C46 C5 C13 C21 C29 C37 C45 C4 C12 C20 C28 C36 C44 C3 C11 C19 C27 C35 C43 C2 C10 C18 C26 C34 C42 C1 C9 C17 C25 C33 C41 BCNT1 BCNT2 BCNT3 BCNT4 BCNT5 BCNT6 Bits 0 to 7 / BERT Count Register Bits 0 to 47 0 = do not select a tap at this bit location / seed value = 0 for this bit position 1 = do select a tap at this bit location / seed value = 1 for this bit position 274 DS26401 Octal T1/E1/J1 Framer 12.11 RAM Access 512 bytes of memory are available for repetitive patterns. This memory is addressed indirectly. Data bytes are loaded one at a time into the Indirect Address register at address 2FFh. The RAM mode control bit, BCR4.3, determines the access to the RAM. If BCR4.3 = 0, the RAM is under control of the BERT state machine. If BCR4.3 = 1, then the RAM is under the control of the parallel port. BCR4.3 = 1 is the topic of this discussion. The accompanying flowchart describes the algorithm used to write repetitive patterns to the RAM. The programmer initializes a counter (n) to -1 in software, then sets BCR4.3 and clears BCR4.4. The rising edge of BCR4.3 resets the RAM address pointer to address 00h. Address 0FFh becomes the indirect access port to the RAM. A write cycle on the parallel port to address 2FFh writes to the address in RAM pointed to by the address pointer. The end of the write cycle, rising edge of WR, will increment the address pointer. The programmer then increments the counter (n) by 1 and loops until the pattern load is complete. Clear BCR4.3 to return control of the RAM to the BERT state machine. Finally, write the value in the counter (n) back to address 2F4h and 2F5h to mark the last address of the pattern in memory. The RAM contents can be verified by executing the same algorithm, replacing the parallel port write with a read and setting BCR4.4. BCR4.3 must remain set for the entire algorithm to properly increment the address pointer. Start BCR4.3=1 BCR4.4=0 n = -1 Write byte to address 2FFh n=n+1 No Last byte ? Yes Write n to BCR3 If n > 255 then set BCR4.0 BCR4.3 = 0 Done 275 DS26401 Octal T1/E1/J1 Framer 13. FUNCTIONAL TIMING 13.1 Delays Table 13-1 shows the delay through the framer with the elastic disabled. With the elastic stores enabled, the delay will be what is shown in the table, plus a variable amount depending on the pointer positions in the elastic store. Table 13-1. Throughput Delays MODE T1 Receive Path T1 Transmit Path E1 Receive Path E1 Transmit Path DELAY 11 RCLKs 16 TCLKs 6 RCLKs 12 TCLKs 276 DS26401 Octal T1/E1/J1 Framer 13.2 T1 Receiver Functional Timing Diagrams Figure 13-1. T1 Receive-Side D4 Timing FRAME# RFSYNC RSYNC 1 RSYNC 2 RSYNC 3 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 NOTE 1: RSYNC IN THE FRAME MODE (RIOCR.0 = 0) AND DOUBLEWIDE FRAME SYNC IS NOT ENABLED (RIOCR.1 = 0). NOTE 2: RSYNC IN THE FRAME MODE (RIOCR.0 = 0) AND DOUBLEWIDE FRAME SYNC IS ENABLED (RIOCR.1 = 1). NOTE 3: RSYNC IN THE MULTIFRAME MODE (RIOCR.0 = 1). Figure 13-2. T1 Receive-Side ESF Timing FRAME# RSYNC 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 RFSYNC RSYNC RSYNC 2 3 NOTE 1: RSYNC IN FRAME MODE (RIOCR.0 = 0) AND DOUBLE -WIDE FRAME SYNC IS NOT ENABLED (RIOCR.1 = 0). NOTE 2: RSYNC IN FRAME MODE (RIOCR.0 = 0) AND DOUBLE- WIDE FRAME SYNC IS ENABLED (RIOCR.1 = 1). NOTE 3: RSYNC IN MULTIFRAME MODE (RIOCR.0 = 1). 277 DS26401 Octal T1/E1/J1 Framer Figure 13-3. T1 Receive-Side Boundary Timing (Elastic Store Disabled) RCLK CHANNEL 23 CHANNEL 24 LSB MSB LSB CHANNEL 1 RSER RSYNC RFSYNC RSIG RCHCLK RCHBLK1 F MSB CHANNEL 23 A B C/A D/B CHANNEL 24 A B C/A D/B CHANNEL 1 A NOTE 1: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24. Figure 13-4. T1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled) RSYSCLK CHANNEL 23 CHANNEL 24 LSB MSB LSB CHANNEL 1 RSER RSYNC1 RMSYNC RSYNC2 RSIG RCHCLK RCHBLK 3 F MSB CHANNEL 23 A B C/A D/B CHANNEL 24 A B C/A D/B CHANNEL 1 A NOTE 1: RSYNC IS IN OUTPUT MODE (RIOCR.2 = 0). NOTE 2: RSYNC IS IN INPUT MODE (RIOCR.2 = 1). NOTE 3: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24. 278 DS26401 Octal T1/E1/J1 Framer Figure 13-5. T1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled) RSYSCLK RSER RSYNC 1 CHANNEL 31 LSB MSB CHANNEL 32 LSB CHANNEL 1 2 RMSYNC RSYNC 3 CHANNEL 31 B C/A D/B CHANNEL 32 B C/A D/B CHANNEL 1 RSIG RCHCLK RCHBLK 4 A A NOTE 1: RSER DATA IN CHANNELS 1, 5, 9, 13, 17, 21, 25, AND 29 ARE FORCED TO 1. NOTE 2: RSYNC IS IN OUTPUT MODE (RIOCR.2 = 0). NOTE 3: RSYNC IS IN INPUT MODE (RIOCR.2 = 1). NOTE 4: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 1. NOTE 5: THE F-BIT POSITION IS PASSED THROUGH THE RECEIVE-SIDE ELASTIC STORE. 279 DS26401 Octal T1/E1/J1 Framer Figure 13-6. T1 Receive-Side Interleave Bus Operation, BYTE Mode RSYNC RSER 1 FR1 CH32 FR1 CH32 FR0 CH1 FR0 CH1 FR1 CH1 FR1 CH1 FR1 CH1 FR1 CH1 FR2 CH1 FR2 CH1 FR3 CH1 FR3 CH1 FR0 CH2 FR0 CH2 FR0 CH2 FR0 CH2 FR1 CH2 FR1 CH2 FR1 CH2 FR1 CH2 FR2 CH2 FR2 CH2 FR3 CH2 FR3 CH2 1 RSIG RSER2 RSIG2 FR2 CH32 FR3 CH32 FR0 CH1 FR2 CH32 FR3 CH32 FR0 CH1 BIT DETAIL SYSCLK RSYNC 3 FRAMER 3, CHANNEL 32 FRAMER 0, CHANNEL 1 LSB MSB FRAMER 1, CHANNEL 1 LSB RSER RSIG A B C LSB MSB FRAMER 3, CHANNEL 32 D FRAMER 0, CHANNEL 1 A B C D FRAMER 1, CHANNEL 1 A B C D NOTE 1: 4.096MHz BUS CONFIGURATION. NOTE 2: 8.192MHz BUS CONFIGURATION. NOTE 3: RSYNC IS IN INPUT MODE (RIOCR.2 = 0). NOTE 4: SHOWS SYSTEM IMPLEMENTATION WITH MULTIPLE 31IP02 CORES DRIVING BACKPLANE. NOTE 5: THOUGH NOT SHOWN, TCHCLK CONTINUES TO MARK THE CHANNEL LSB FOR THE FRAMER'S ACTIVE PERIOD. NOTE 6: THOUGH NOT SHOWN, TCHBLK CONTINUES TO MARK THE BLOCKED CHANNELS FOR THE FRAMERS ACTIVE PERIOD. 280 DS26401 Octal T1/E1/J1 Framer Figure 13-7. T1 Receive-Side Interleave Bus Operation, FRAME Mode RSYNC RSER 1 FR1 CH1-32 FR1 CH1-32 FR0 CH1-32 FR0 CH1-32 FR1 CH1-32 FR1 CH1-32 FR0 CH1-32 FR0 CH1-32 FR1 CH1-32 FR1 CH1-32 1 RSIG RSER2 RSIG2 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 BIT DETAIL SYSCLK RSYNC 3 FRAMER 3, CHANNEL 32 FRAMER 0, CHANNEL 1 LSB MSB FRAMER 0, CHANNEL 2 LSB RSER RSIG A B LSB MSB FRAMER 3, CHANNEL 32 C/A D/B FRAMER 0, CHANNEL 1 A B C/A D/B FRAMER 0, CHANNEL 2 A B C/A D/B NOTE 1: 4.096MHz BUS CONFIGURATION. NOTE 2: 8.192MHz BUS CONFIGURATION. NOTE 3: RSYNC IS IN THE INPUT MODE (RIOCR.2 = 0). NOTE 4: SHOWS SYSTEM IMPLEMENTATION WITH MULTIPLE 31IP02 CORES DRIVING BACKPLANE. NOTE 5: THOUGH NOT SHOWN, RCHCLK CONTINUES TO MARK THE CHANNEL LSB FOR THE FRAMER'S ACTIVE PERIOD. NOTE 6: THOUGH NOT SHOWN, RCHBLK CONTINUES TO MARK THE BLOCKED CHANNELS FOR THE FRAMERS ACTIVE PERIOD. 281 DS26401 Octal T1/E1/J1 Framer 13.3 T1 Transmitter Functional Timing Diagrams Figure 13-8. T1 Transmit-Side D4 Timing FRAME# TSYNC 1 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 TSSYNC TSYNC TSYNC 2 3 NOTE 1: TSYNC IN THE FRAME MODE (TIOCR.0 = 0) AND DOUBLEWIDE FRAME SYNC IS NOT ENABLED (TIOCR.1 = 0). NOTE 2: TSYNC IN THE FRAME MODE (TIOCR.0 = 0) AND DOUBLEWIDE FRAME SYNC IS ENABLED (TIOCR.1 = 1). NOTE 3: TSYNC IN THE MULTIFRAME MODE (TIOCR.0 = 1). Figure 13-9. T1 Transmit-Side ESF Timing FRAME# TSYNC1 TSSYNC TSYNC 2 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 TSYNC NOTE 1: TSYNC IN FRAME MODE (TIOCR.0 = 0) AND DOUBLEWIDE FRAME SYNC IS NOT ENABLED (TIOCR.1 = 0). NOTE 2: TSYNC IN FRAME MODE (TIOCR.0 = 0) AND DOUBLEWIDE FRAME SYNC IS ENABLED (TIOCR.1 = 1). NOTE 3: TSYNC IN MULTIFRAME MODE (TIOCR.0 = 1). 282 DS26401 Octal T1/E1/J1 Framer Figure 13-10. T1 Transmit-Side Boundary Timing (Elastic Store Disabled) TCLK CHANNEL 1 CHANNEL 2 LSB MSB LSB MSB TSER TSYNC1 TSYNC2 LSB F MSB CHANNEL 1 CHANNEL 2 C/A D/B A B C/A D/B TSIG TCHCLK TCHBLK 3 D/B A B NOTE 1: TSYNC IS IN THE OUTPUT MODE (TIOCR.2 = 1). NOTE 2: TSYNC IS IN THE INPUT MODE (TIOCR.2 = 0). NOTE 3: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 2. Figure 13-11. T1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled) TSYSCLK CHANNEL 23 CHANNEL 24 LSB MSB LSB F MSB CHANNEL 1 TSER TSSYNC CHANNEL 23 CHANNEL 24 C/A D/B A B C/A D/B CHANNEL 1 A TSIG TCHCLK TCHBLK 1 A B NOTE 1: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24. 283 DS26401 Octal T1/E1/J1 Framer Figure 13-12. T1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled) TSYSCLK CHANNEL 31 CHANNEL 32 LSB MSB LSB CHANNEL 1 TSER 1 F 4 TSSYNC CHANNEL 31 CHANNEL 32 C/A D/B A B C/A D/B CHANNEL 1 A TSIG TCHCLK TCHBLK 2 A B NOTE 1: TSER DATA IN CHANNELS 1, 5, 9, 13, 17, 21, 25, AND 29 IS IGNORED. NOTE 2: TCHBLK IS PROGRAMMED TO BLOCK CHANNELS 31 AND 1. NOTE 3: THE F-BIT POSITION FOR THE T1 FRAME IS SAMPLED AND PASSED THROUGH THE TRANSMIT-SIDE ELASTIC STORE INTO THE MSB BIT POSITION OF CHANNEL 1. (NORMALLY, THE TRANSMIT-SIDE FORMATTER OVERWRITES THE F-BIT POSITION UNLESS THE FORMATTER IS PROGRAMMED TO PASS-THROUGH THE F-BIT POSITION.) Figure 13-13. T1 Transmit-Side Interleave Bus Operation, BYTE Mode TSYNC TSER 1 FR 1 C H32 FR 1 C H32 FR0 CH1 FR0 CH1 FR1 C H1 FR1 C H1 FR1 CH1 FR1 CH1 FR2 C H1 FR2 C H1 FR3 CH 1 FR3 CH 1 FR 0 C H2 FR 0 C H2 FR 0 CH 2 FR 0 CH 2 FR 1 CH 2 FR 1 CH 2 FR1 CH2 FR1 CH2 FR2 CH2 FR2 CH2 FR3 C H2 FR3 C H2 TSIG1 TSER2 TSIG 2 FR 2 CH 32 FR 3 CH 32 FR0 CH1 FR 2 CH 32 FR 3 CH 32 FR0 CH1 BIT DETAIL SYSCLK TSYNC 3 FRAMER 3, CHANNEL 32 FRAMER 0, CHANNEL 1 MSB LSB MSB FRAMER 1, CHANNEL 1 LSB TSER TSIG A B C/A LSB FRAMER 3, CHANNEL 32 D/B FRAMER 0, CHANNEL 1 A B C/A D/B FRAMER 1, CHANNEL 1 A B C/A D /B NOTE 1: 4.096MHz BUS CONFIGURATION. NOTE 2: 8.192MHz BUS CONFIGURATION. NOTE 3: TSYNC IS IN THE INPUT MODE (TIOCR.2 = 0). NOTE 4: THOUGH NOT SHOWN, TCHCLK CONTINUES TO MARK THE CHANNEL LSB FOR THE FRAMER'S ACTIVE PERIOD. NOTE 5: THOUGH NOT SHOWN, TCHBLK CONTINUES TO MARK THE BLOCKED CHANNELS FOR THE FRAMERS ACTIVE PERIOD. 284 DS26401 Octal T1/E1/J1 Framer Figure 13-14. T1 Transmit Interleave Bus Operation, FRAME Mode TSYNC TSER 1 FR1 CH1-32 FR1 CH1-32 FR0 CH1-32 FR0 CH1-32 FR1 CH1-32 FR1 CH1-32 FR0 CH1-32 FR0 CH1-32 FR1 CH1-32 FR1 CH1-32 TSIG1 TSER2 TSIG2 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 BIT DETAIL SYSCLK TSYNC 3 FRAMER 3, CHANNEL 32 FRAMER 0, CHANNEL 1 LSB MSB FRAMER 0, CHANNEL 2 LSB TSER TSIG A B LSB MSB FRAMER 3, CHANNEL 32 C/A D/B FRAMER 0, CHANNEL 1 A B C/A D/B FRAMER 0, CHANNEL 2 A B C/A D/B NOTE 1: 4.096MHz BUS CONFIGURATION. NOTE 2: 8.192MHz BUS CONFIGURATION. NOTE 3: TSYNC IS IN THE INPUT MODE (TIOCR.2 = 0). NOTE 4: THOUGH NOT SHOWN, TCHCLK CONTINUES TO MARK THE CHANNEL LSB FOR THE FRAMER'S ACTIVE PERIOD. NOTE 5: THOUGH NOT SHOWN, TCHBLK CONTINUES TO MARK THE BLOCKED CHANNELS FOR THE FRAMERS ACTIVE PERIOD. 285 DS26401 Octal T1/E1/J1 Framer 13.4 E1 Receiver Functional Timing Diagrams Figure 13-15. E1 Receive-Side Timing FRAME# RFSYNC RSYNC 1 RSYNC 2 NOTE 1: RSYNC IN FRAME MODE (RIOCR.0 = 0). NOTE 2: RSYNC IN MULTIFRAME MODE (RIOCR.0 = 1). NOTE 3: THIS DIAGRAM ASSUMES THE CAS MF BEGINS IN THE RAF FRAME. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 Figure 13-16. E1 Receive-Side Boundary Timing (Elastic Store Disabled) RCLK CHANNEL 32 CHANNEL 1 LSB CHANNEL 2 RSER RSYNC RFSYNC CHANNEL 32 Si 1 A Sa4 Sa5 Sa6 Sa7 Sa8 MSB CHANNEL 1 C D Note 3 RSIG RCHCLK RCHBLK 1 A B CHANNEL 2 A B NOTE 1: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 1. NOTE 2: SHOWN IS A RNAF FRAME BOUNDARY. NOTE 3: RSIG NORMALLY CONTAINS THE CAS MULTIFRAME ALIGNMENT NIBBLE (0000) IN CHANNEL 1. 286 DS26401 Octal T1/E1/J1 Framer Figure 13-17. E1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled) RSYSCLK CHANNEL 23/31 CHANNEL 24/32 LSB CHANNEL 1/2 RSER 1 LSB MSB F MSB RSYNC2 RMSYNC RSYNC 3 RCHCLK RCHBLK 4 NOTE 1: DATA FROM THE E1 CHANNELS 1. 5. 9, 13, 17, 21, 25, AND 29 IS DROPPED (CHANNEL 2 FROM THE E1 LINK IS (MAPPED TO CHANNEL 1 OF THE T1 LINK, ETC.) AND THE F-BIT POSITION IS ADDED (FORCED TO 1). NOTE 2: RSYNC IS IN OUTPUT MODE (RIOCR.2 = 0). NOTE 3: RSYNC IS IN INPUT MODE (RIOCR.2 = 1). NOTE 4: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24. Figure 13-18. E1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled) RSYSCLK CHANNEL 31 CHANNEL 32 LSB MSB LSB MSB CHANNEL 1 RSER RSYNC1 RMSYNC RSYNC 2 RSIG RCHCLK RCHBLK 3 A CHANNEL 31 C B D A CHANNEL 32 C B D CHANNEL 1 Note 4 NOTE 1: RSYNC IS IN OUTPUT MODE (RIOCR.2 = 0). NOTE 2: RSYNC IS IN INPUT MODE (RIOCR.2 = 1). NOTE 3: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 1. NOTE 4: RSIG NORMALLY CONTAINS THE CAS MULTIFRAME ALIGNMENT NIBBLE (0000) IN CHANNEL 1. 287 DS26401 Octal T1/E1/J1 Framer 13.5 E1 Transmitter Functional Timing Diagrams Figure 13-19. E1 Transmit-Side Timing FRAME# TSYNC 1 14 15 16 1 2 3 4 56 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 TSSYNC TSYNC 2 NOTE 1: TSYNC IS IN FRAME MODE (TIOCR.0 = 0). NOTE 2: TSYNC IS IN MULTIFRAME MODE (TIOCR.0 = 1). NOTE 3: THIS DIAGRAM ASSUMES BOTH THE CAS MF AND THE CRC4 MF BEGIN WITH THE TAF FRAME. Figure 13-20. E1 Transmit-Side Boundary Timing (Elastic Store Disabled) TCLK CHANNEL 1 CHANNEL 2 LSB MSB TSER TSYNC1 TSYNC2 LSB Si 1 A Sa4 Sa5 Sa6 Sa7 Sa8 MSB CHANNEL 1 CHANNEL 2 A B C D TSIG TCHCLK TCHBLK 3 D NOTE 1: TSYNC IS IN OUTPUT MODE (TIOCR.2 = 1). NOTE 2: TSYNC IS IN INPUT MODE (TIOCR.2 = 0). NOTE 3: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 2. NOTE 4: THE SIGNALING DATA AT TSIG DURING CHANNEL 1 IS NORMALLY OVERWRITTEN IN THE TRANSMIT FORMATTER WITH THE CAS MF ALIGNMENT NIBBLE (0000). NOTE 5: SHOWN IS A TNAF FRAME BOUNDARY. 288 DS26401 Octal T1/E1/J1 Framer Figure 13-21. E1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled) TSYSCLK CHANNEL 23 CHANNEL 24 LSB MSB LSB F MSB CHANNEL 1 TSER 1 TSSYNC TCHCLK TCHBLK 2 NOTE 1: THE F-BIT POSITION IN THE TSER DATA IS IGNORED. NOTE 2: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24. Figure 13-22. E1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled) TSYSCLK CHANNEL 31 CHANNEL 32 LSB MSB LSB MSB CHANNEL 1 TSER TSYNC 1 TSIG TCHCLK TCHBLK 2 A CHANNEL 31 C B D A CHANNEL 32 C B D CHANNEL 1 NOTE 1: TSYNC IS IN INPUT MODE (TIOCR.2 = 0). NOTE 2: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 1. 289 DS26401 Octal T1/E1/J1 Framer Figure 13-23. E1 G.802 Timing TS # RSYNC TSYNC RCHCLK TCHCLK RCHBLK TCHBLK 31 32 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 RCLK / RSYSCLK TCLK / TSYSCLK CHANNEL 25 RSER / TSER RCHCLK / TCHCLK RCHBLK / TCHBLK LSB MSB CHANNEL 26 NOTE: RCHBLK OR TCHBLK PROGRAMMED TO PULSE HIGH DURING TIME SLOTS 1 THROUGH 15, 17 THROUGH 25, AND BIT 1 OF TIME SLOT 26. 290 DS26401 Octal T1/E1/J1 Framer 14. OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Lead with Respect to VSS (except VDD) Supply Voltage (VDD) Range with Respect to VSS Operating Temperature Range for DS26401 Operating Temperature Range for DS26401N Storage Temperature Range Soldering Temperature -0.3V to +5.5V -0.3V to +3.63V 0C to +70C -40C to +85C -55C to +125C See IPC/JEDEC J-STD-020A Specification This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS (TA = -40C to +85C for DS26401N.) PARAMETER Logic 1 Logic 0 Supply SYMBOL VIH VIL VDD CONDITIONS MIN 2.0 -0.3 3.135 3.3 TYP MAX 5.5 +0.8 3.465 UNITS V V V CAPACITANCE (TA = +25C) PARAMETER Input Capacitance Output Capacitance SYMBOL CIN COUT CONDITIONS MIN TYP 7 7 MAX UNITS pF pF DC CHARACTERISTICS (VDD = 3.135V to 3.465V, TA = -40C to +85C.) PARAMETER Supply Current at 3.3V Input Leakage Input Leakage on Pins with Pullups Tri-State Output Leakage Output Voltage SYMBOL IDD IIL IL IOL VOH VOL Io = -4.0mA Io = +4.0mA CONDITIONS (Note 1) -10.0 -500 -10.0 2.4 0.4 MIN TYP 275 MAX 330 +10.0 +500 +10.0 UNITS mA mA mA mA V Note 1: RCLK1-n = TCLK1-n = 2.048MHz, GCLK = 45MHz. 291 DS26401 Octal T1/E1/J1 Framer 15. TIMING Unless otherwise noted, all timing numbers assume 20pF test load on output signals, 40pF test load on bus signals. 15.1 Microprocessor Bus AC Characteristics AC CHARACTERISTICS--MICROPROCESSOR BUS TIMING (VDD = 3.3V 5%, TA = 0C to +70C for DS26401; VDD = 3.3V 5%, TA = -40C to +85C for DS26401N.) (Figure 15-1, Figure 15-2, Figure 15-3, and Figure 15-4) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Setup Time for A[11:0] Valid to CS Active Setup Time for CS Active to Either RD or WR Active Delay Time from Either RD or DS Active to D[7:0] Valid Hold Time from Either RD or WR Inactive to CS Inactive Hold Time from CS or RD or DS Inactive to D[7:0] Tri-State Wait Time from WR Active to Latch Data Data Set Up Time to WR Inactive Data Hold Time from WR Inactive Address Hold from WR Inactive Write Access to Subsequent Write/Read Access Delay Time Note 1: Guaranteed by design. t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 (Note 1) (Note 1) 0 0 115 0 2.5 35 10 2 3 80 20 ns ns ns ns ns ns ns ns ns ns 292 DS26401 Octal T1/E1/J1 Framer Figure 15-1. Intel Bus Read Timing (BTS = 0) t9 ADDR[11:0] DATA[7:0] WR Address Valid Data Valid t5 t1 CS t2 t3 t4 t10 RD Figure 15-2. Intel Bus Write Timing (BTS = 0) t9 ADDR[11:0] DATA[7:0] Address Valid t7 t8 RD t1 CS t2 t6 t4 t10 WR 293 DS26401 Octal T1/E1/J1 Framer Figure 15-3. Motorola Bus Read Timing (BTS = 1) t9 ADDR[11:0] DATA[7:0] R/W Address Valid Data Valid t5 t1 CS t2 t3 t4 t10 DS Figure 15-4. Motorola Bus Write Timing (BTS = 1) t9 ADDR[11:0] DATA[7:0] Address Valid t7 t8 R/W t1 CS t2 t6 t4 t10 DS 294 DS26401 Octal T1/E1/J1 Framer 15.2 Receiver AC Characteristics RECEIVER AC CHARACTERISTICS (VDD = 3.3V 5%, TA = -40C to +85C.) (Note 1: Guaranteed by design. Figure 15-5, Figure 15-6, and Figure 15-7) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS RCLK Period tCP tCP T1 mode E1 mode 85 648 ns 488 ns 85 RCLK Pulse Width tCH tCL RSYSCLK Period (Note 1) tSP tSP RSYSCLK = 1.544MHz RSYSCLK = 2.048MHz 60 60 30 648 ns 488 ns RSYSCLK Pulse Width RSYNC Setup to RSYSCLK Falling RSYNC Pulse Width RPOS/RNEG Setup to RCLK Falling RPOS/RNEG Hold From RCLK Falling Delay RCLK to RSER, RSIG Valid Delay RCLK to RCHCLK, RSYNC, RCHBLK, RFSYNC Delay RSYSCLK to RSER, RSIG Valid Delay RSYSCLK to RCHCLK, RCHBLK, RMSYNC, RSYNC Note 1: Guaranteed by design. tSH tSL tSU tPW tSU tHD tD1 tD2 tD3 tD4 30 20 50 20 20 50 50 50 50 tSH - 5 ns ns ns ns ns ns ns ns 295 DS26401 Octal T1/E1/J1 Framer Figure 15-5. Receive Framer Timing--Backplane (T1 Mode) RCLK t D1 RSER / RSIG t D2 F-Bit RCHCLK t D2 RCHBLK t D2 RFSYNC / RMSYNC t D2 RSYNC 1 NOTE 1: RSYNC IS IN OUTPUT MODE. NOTE 2: NO RELATIONSHIP BETWEEN RCHCLK AND RCHBLK AND OTHER SIGNALS IS IMPLIED. Figure 15-6. Receive-Side Timing--Elastic Store Enabled (T1 Mode) t SL t SH t SP SEE NOTE 3 t D4 RSYSCLK t D3 RSER / RSIG RCHCLK t D4 RCHBLK t D4 RMSYNC RSYNC 1 2 t D4 t HD t SU RSYNC NOTE 1: RSYNC IS IN OUTPUT MODE. NOTE 2: RSYNC IS IN INPUT MODE. NOTE 3: F-BIT WHEN RIOCR.4 = 0, MSB OF TS0 WHEN RIOCR.4 = 1. 296 DS26401 Octal T1/E1/J1 Framer Figure 15-7. Receive Framer Timing--Line Side t CL RCLK t SU RPOS, RNEG t HD t CH t CP 297 DS26401 Octal T1/E1/J1 Framer 15.3 Transmit AC Characteristics TRANSMIT AC CHARACTERISTICS (VDD = 3.3V 5%, TA = -40C to +85C.) (Figure 15-8, Figure 15-9, and Figure 15-10) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS tCP TCLK Period tCP tCH tCL tSP TSYSCLK Period (Note 1) tSP tSH tSL tSU tPW tSU tHD tD2 tD3 tD4 T1 mode E1 mode 85 85 RSYSCLK = 1.544MHz RSYSCLK = 2.048MHz 60 60 30 30 20 50 20 20 648 488 ns TCLK Pulse Width ns 648 448 ns TSYSCLK Pulse Width TSYNC or TSSYNC Setup to TCLK or TSYSCLK falling TSYNC or TSSYNC Pulse Width TSER, TSIG, Setup to TCLK, TSYSCLK Falling TSER, TSIG, Hold from TCLK, TSYSCLK Falling Delay TCLK to TCHBLK, TCHCLK, TSYNC Delay TSYSCLK to TCHCLK, TCHBLK Delay TCLK to TPOS, TNEG Note 1: Guaranteed by design. ns tCH - 5 or tSH - 5 ns ns ns ns 50 50 50 ns ns ns 298 DS26401 Octal T1/E1/J1 Framer Figure 15-8. Transmit Formatter Timing--Backplane t CP t CL TCLK t D1 TESO t SU TSER / TSIG t D2 TCHCLK TCHBLK t D2 TSYNC1 t SU TSYNC2 NOTE 1: TSYNC IS IN OUTPUT MODE. NOTE 2: TSYNC IS IN INPUT MODE. NOTE 3: TSER IS SAMPLED ON THE FALLING EDGE OF TCLK WHEN THE TRANSMIT-SIDE ELASTIC STORE IS DISABLED. NOTE 4: TCHCLK AND TCHBLK ARE SYNCHRONOUS WITH TCLK WHEN THE TRANSMIT-SIDE ELASTIC STORE IS DISABLED. NOTE 5: NO RELATIONSHIP BETWEEN TCHCLK AND TCHBLK AND THE OTHER SIGNALS IS IMPLIED. t CH t HD t D2 t HD 299 DS26401 Octal T1/E1/J1 Framer Figure 15-9. Transmit Formatter Timing, Elastic Store Enabled t SP t SL TSYSCLK t SU TSER t D3 TCHCLK t D3 TCHBLK t SU TSSYNC t HD t HD t SH NOTE 1: TSER IS ONLY SAMPLED ON THE FALLING EDGE OF TSYSCLK WHEN THE TRANSMIT-SIDE ELASTIC STORE IS ENABLED. NOTE 2: TCHCLK AND TCHBLK ARE SYNCHRONOUS WITH TSYSCLK WHEN THE TRANSMIT-SIDE ELASTIC STORE IS ENABLED. Figure 15-10. Transmit Formatter Timing--Line Side t CP t CL TCLK t CH TPOS, TNEG t D3 300 DS26401 Octal T1/E1/J1 Framer 15.4 JTAG Interface Timing JTAG INTERFACE TIMING (VDD = 3.3V 5%, TA = -40C to +85C.) (Figure 15-11) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS JTCLK Clock Period JTCLK Clock High/Low Time JTCLK to JTDI, JTMS Setup Time JTCLK to JTDI, JTMS Hold Time JTCLK to JTDO Delay JTCLK to JTDO High-Z Delay JTRST Width Low Time Note 1: Clock can be stopped high or low. t1 t2/t3 t4 t5 t6 t7 t8 (Note 1) 50 3 2 2 2 100 1000 500 50 50 ns ns ns ns ns ns ns Figure 15-11. JTAG Interface Timing Diagram t1 t2 t3 JTCLK t4 JTDI, JTMS, JTRST t6 t7 t5 JTD0 t8 JTRST 15.5 System Clock AC Characteristics SYSTEM CLOCK AC CHARACTERISTICS PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS REF_CLK Frequency REF_CLK Duty Cycle GCLK Frequency GCLK Duty Cycle Note 1: Guaranteed by design. 1.544 2.048 (Note 1) (Note 1) 40 43 40 45 60 49 60 MHz % MHz % 301 DS26401 Octal T1/E1/J1 Framer 16. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT The DS26401 IEEE 1149.1 design supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE (see Table 16-1). The DS26401 contains the following, as required by IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture: Test Access Port (TAP) TAP Controller Instruction Register Bypass Register Boundary Scan Register Device Identification Register The Test Access Port has the necessary interface pins JTRST, JTCLK, JTMS, JTDI, and JTDO. See the pin descriptions for details. Figure 16-1. JTAG Functional Block Diagram BOUNDRY SCAN REGISTER IDENTIFICATION REGISTER BYPASS REGISTER INSTRUCTION REGISTER TEST ACCESS PORT CONTROLLER VDD 10kW MUX SELECT OUTPUT ENABLE VDD 10kW VDD 10kW JTDI JTMS JTCLK JTRST JTDO 302 DS26401 Octal T1/E1/J1 Framer 16.1 TAP Controller State Machine The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK. See Figure 16-2. Figure 16-2. Tap Controller State Diagram 1 Test Logic Reset 0 Run Test/ Idle 1 Select DR-Scan 0 1 Capture DR 0 Shift DR 1 Exit DR 0 Pause DR 1 0 Exit2 DR 1 Update DR 1 0 0 0 1 0 1 1 Select IR-Scan 0 Capture IR 0 Shift IR 1 Exit IR 0 Pause IR 1 Exit2 IR 1 Update IR 1 0 0 1 0 1 0 303 DS26401 Octal T1/E1/J1 Framer Test-Logic-Reset Upon power up, the TAP Controller will be in the Test-Logic-Reset state. The Instruction register will contain the IDCODE instruction. All system logic of the device will operate normally. Run-Test-Idle The Run-Test-Idle is used between scan operations or during specific tests. The Instruction register and test registers will remain idle. Select-DR-Scan All test registers retain their previous state. With JTMS LOW, a rising edge of JTCLK moves the controller into the Capture-DR state and will initiate a scan sequence. JTMS HIGH during a rising edge on JTCLK moves the controller to the Select-IR-Scan state. Capture-DR Data may be parallel-loaded into the test data registers selected by the current instruction. If the instruction does not call for a parallel load or the selected register does not allow parallel loads, the test register will remain at its current value. On the rising edge of JTCLK, the controller will go to the Shift-DR state if JTMS is LOW or it will go to the Exit1-DR state if JTMS is HIGH. Shift-DR The test data register selected by the current instruction will be connected between JTDI and JTDO and will shift data one stage towards its serial output on each rising edge of JTCLK. If a test register selected by the current instruction is not placed in the serial path, it will maintain its previous state. Exit1-DR While in this state, a rising edge on JTCLK will put the controller in the Update-DR state, which terminates the scanning process, if JTMS is HIGH. A rising edge on JTCLK with JTMS LOW will put the controller in the Pause-DR state. Pause-DR Shifting of the test registers is halted while in this state. All test registers selected by the current instruction will retain their previous state. The controller will remain in this state while JTMS is LOW. A rising edge on JTCLK with JTMS HIGH will put the controller in the Exit2-DR state. Exit2-DR A rising edge on JTCLK with JTMS HIGH while in this state will put the controller in the Update-DR state and terminate the scanning process. A rising edge on JTCLK with JTMS LOW will enter the Shift-DR state. Update-DR A falling edge on JTCLK while in the Update-DR state will latch the data from the shift register path of the test registers into the data output latches. This prevents changes at the parallel output due to changes in the shift register. Select-IR-Scan All test registers retain their previous state. The instruction register will remain unchanged during this state. With JTMS LOW, a rising edge on JTCLK moves the controller into the Capture-IR state and will initiate a scan sequence for the instruction register. JTMS HIGH during a rising edge on JTCLK puts the controller back into the Test-Logic-Reset state. Capture-IR The Capture-IR state is used to load the shift register in the instruction register with a fixed value. This value is loaded on the rising edge of JTCLK. If JTMS is HIGH on the rising edge of JTCLK, the controller will enter the Exit1IR state. If JTMS is LOW on the rising edge of JTCLK, the controller will enter the Shift-IR state. Shift-IR In this state, the shift register in the instruction register is connected between JTDI and JTDO and shifts data one stage for every rising edge of JTCLK towards the serial output. The parallel register and all test registers remain at their previous states. A rising edge on JTCLK with JTMS HIGH will move the controller to the Exit1-IR state. A 304 DS26401 Octal T1/E1/J1 Framer rising edge on JTCLK with JTMS LOW will keep the controller in the Shift-IR state while moving data one stage thorough the instruction shift register. Exit1-IR A rising edge on JTCLK with JTMS LOW will put the controller in the Pause-IR state. If JTMS is HIGH on the rising edge of JTCLK, the controller will enter the Update-IR state and terminate the scanning process. Pause-IR Shifting of the instruction shift register is halted temporarily. With JTMS HIGH, a rising edge on JTCLK will put the controller in the Exit2-IR state. The controller will remain in the Pause-IR state if JTMS is LOW during a rising edge on JTCLK. Exit2-IR A rising edge on JTCLK with JTMS LOW will put the controller in the Update-IR state. The controller will loop back to Shift-IR if JTMS is HIGH during a rising edge of JTCLK in this state. Update-IR The instruction code shifted into the instruction shift register is latched into the parallel output on the falling edge of JTCLK as the controller enters this state. Once latched, this instruction becomes the current instruction. A rising edge on JTCLK with JTMS LOW puts the controller in the Run-Test-Idle state. With JTMS HIGH, the controller enters the Select-DR-Scan state. 305 DS26401 Octal T1/E1/J1 Framer 16.2 Instruction Register The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the TAP controller enters the Shift-IR state, the instruction shift register will be connected between JTDI and JTDO. While in the Shift-IR state, a rising edge on JTCLK with JTMS LOW will shift the data one stage towards the serial output at JTDO. A rising edge on JTCLK in the Exit1-IR state or the Exit2-IR state with JTMS HIGH will move the controller to the Update-IR state. The falling edge of that same JTCLK will latch the data in the instruction shift register to the instruction parallel output. Instructions supported by the DS26401 and its respective operational binary codes are shown in Table 16-1. Table 16-1. Instruction Codes for IEEE 1149.1 Architecture INSTRUCTION SAMPLE/PRELOAD BYPASS EXTEST CLAMP HIGHZ IDCODE SELECTED REGISTER Boundary Scan Bypass Boundary Scan Bypass Bypass Device Identification INSTRUCTION CODES 010 111 000 011 100 001 SAMPLE/PRELOAD This is a mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions. The digital I/Os of the device can be sampled at the boundary scan register without interfering with the normal operation of the device by using the Capture-DR state. SAMPLE/PRELOAD also allows the device to shift data into the boundary scan register via JTDI using the Shift-DR state. BYPASS When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO through the one-bit bypass test register. This allows data to pass from JTDI to JTDO not affecting the device's normal operation. EXTEST This allows testing of all interconnections to the device. When the EXTEST instruction is latched in the instruction register, the following actions occur. Once enabled via the Update-IR state, the parallel outputs of all digital output pins will be driven. The boundary scan register will be connected between JTDI and JTDO. The Capture-DR will sample all digital inputs into the boundary scan register. CLAMP All digital outputs of the device will output data from the boundary scan parallel output while connecting the bypass register between JTDI and JTDO. The outputs will not change during the CLAMP instruction. HIGHZ All digital outputs of the device will be placed in a high impedance state. The BYPASS register will be connected between JTDI and JTDO. IDCODE When the IDCODE instruction is latched into the parallel instruction register, the identification test register is selected. The device identification code will be loaded into the identification register on the rising edge of JTCLK following entry into the Capture-DR state. Shift-DR can be used to shift the identification code out serially via JTDO. During Test-Logic-Reset, the identification code is forced into the instruction register's parallel output. The ID code will always have a `1' in the LSB position. The next 11 bits identify the manufacturer's JEDEC number and number of continuation bytes followed by 16 bits for the device and 4 bits for the version. 306 DS26401 Octal T1/E1/J1 Framer Table 16-2. ID Code Structure MSB Version (contact factory) 4 bits Device ID (0025h) 0000000000100101 JEDEC 00010100001 LSB (Must be '1') 1 1 16.3 Test Registers IEEE 1149.1 requires a minimum of two test registers--the bypass register and the boundary scan register. An optional test register, the identification register, has been included with the DS26401 design. The identification register is used in conjunction with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller. Boundary Scan Register This register contains a shift register path and a latched parallel output for all control cells and digital I/O cells. It is n bits in length. Bypass Register The bypass register is a single one-bit shift register used with the BYPASS, CLAMP, and HIGHZ instructions, which provides a short path between JTDI and JTDO. Identification Register The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register is selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state. 307 DS26401 Octal T1/E1/J1 Framer 17. PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.) NOTES: 1. 2. 3. 4. 5. DIMENSION IS MM. THE BASIC SOLDER BALL GRID PITCH IS 1.00 MM. DIMENSION IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO PRIMARY DATUM C. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. A1 BALL PAD CORNER ID 308 DS26401 Octal T1/E1/J1 Framer 18. THERMAL INFORMATION PARAMETER Target Ambient Temperature Range Die Junction Temperature Range VALUE -40C to +85C -40C to +125C 19. REVISION HISTORY REVISION 072403 DESCRIPTION New product release. Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time. Ma x i m I n t e g r a t e d P r o d u c t s , 1 2 0 S a n G a b r i e l D r i v e , S u n n y v a l e , C A 9 4 0 8 6 4 0 8 - 7 3 7 - 7 6 0 0 (c) 2003 Maxim Integrated Products * Printed USA 309 |
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